P. Pirsch

Peter Pirsch, G. Meyer, J. P. Wittenburg, 1999, 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461).

Synthetic aperture radar with fast factorized backprojection: a scalable, platform independent architecture for exhaustive FPGA resource utilization

Holger Blume, Peter Pirsch, F. Cholewa, 2017 .

High Performance and Low Power Architectures: GPU vs. FPGA for Fast Factorized Backprojection

Peter Pirsch, Holger Blume, M. Wielage, 2017, 2017 Fifth International Symposium on Computing and Networking (CANDAR).

An FPGA architecture for velocity independent backprojection in FMCW-based SAR systems

Peter Pirsch, Holger Blume, M. Wielage, 2016, 2016 IEEE International Symposium on Signal Processing and Information Technology (ISSPIT).

VLSI architectures for multimedia

Peter Pirsch, H.-J. Stolberg, P. Pirsch, 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

Architecture of an image rendering co-processor for MPEG-4 systems

Christoph Heer, Peter Pirsch, Mladen Berekovic, 2000, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors.

A video signal processor for MIMD multiprocessing

Peter Pirsch, Klaus Herrmann, Jörg Hilgenstock, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architectures

Peter Pirsch, Holger Blume, Guillermo Payá Vayá, 2010, ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors.

Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures

Peter Pirsch, Holger Blume, Ingo Schmädecke, 2009, 2009 International Symposium on Systems, Architectures, Modeling, and Simulation.

RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip

Peter Pirsch, Guillermo Payá Vayá, Javier Martín-Langerwerf, 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration

Peter Pirsch, Guillermo Payá Vayá, Javier Martín-Langerwerf, 2005, SAMOS.

Multicore system-on-chip architecture for MPEG-4 streaming video

Peter Pirsch, Mladen Berekovic, Hans-Joachim Stolberg, 2002, IEEE Trans. Circuits Syst. Video Technol..

A core generator for fully synthesizable and highly parameterizable RISC-cores for system-on-chip designs

Peter Pirsch, Mladen Berekovic, D. Heistermann, 1998, 1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374).

An Algorithm-Hardware-System Approach to VLIW Multimedia Processors

Peter Pirsch, Mladen Berekovic, Johannes Kneip, 1997, Proceedings of First Signal Processing Society Workshop on Multimedia Signal Processing.

Architecture and C++-programming environment of a highly parallel image signal processor

Peter Pirsch, Martin Ohmacht, Johannes Kneip, 1995, Microprocess. Microprogramming.

Parallelization resources of image processing algorithms and their mapping on a programmable parallel videosignal processor

Peter Pirsch, Johannes Kneip, Karsten Rönner, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

On the Benefit of Caching Traffic Flow Data in the Link Buffer

Peter Pirsch, Christian Grimm, Konstantin Septinus, 2008, SAMOS.

Heterogeneous multiprocessor scheduling and allocation using evolutionary algorithms

Peter Pirsch, Carsten Reuter, Markus Schwiegershausen, 1997, Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors.

Compact hardware realization for Hough based extraction of line segments in image sequences for vehicle guidance

Peter Pirsch, Jörg Schönfeld, P. Pirsch, 1993, 1993 IEEE International Conference on Acoustics, Speech, and Signal Processing.

Implementation of a multiprocessor system with distributed embedded DRAM on a large area integrated circuit

Peter Pirsch, Klaus Herrmann, Jörg Hilgenstock, 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

A 1.3 GOPS parallel DSP for high performance image processing applications

K. Ronner, J. Kneip, P. Pirsch, 2000, Proceedings of the 25th European Solid-State Circuits Conference.

A flexible processor architecture for MPEG-4 image compositing

Peter Pirsch, Mladen Berekovic, Rainer Frase, 1998, Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181).

A VLSI based MIMD architecture of a multiprocessor system for real-time video processing applications

Peter Pirsch, Klaus Gaedke, Hartwig Jeschke, 1993, J. VLSI Signal Process..

VLSI Architectures for Digital Video Signal Processing

Peter Pirsch, P. Pirsch, 1992 .

Synthesis of intermediate memories for the data supply to processor arrays

Peter Pirsch, Markus Schwiegershausen, Mirjam Schönfeld, 1992, Algorithms and Parallel VLSI Architectures.

A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications

Peter Pirsch, Mladen Berekovic, Hans-Joachim Stolberg, 2005, J. VLSI Signal Process..

Real-time stereo vision system using semi-global matching disparity estimation: Architecture and FPGA-implementation

Peter Pirsch, Holger Blume, Holger Flatt, 2010, 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.