Y. Hayami

Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

N. Horiguchi, T. Yamamoto, S. Satoh, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

High-Performance Low Operation Power Transistor for 45nm Node Universal Applications

T. Sugii, T. Aoyama, H. Morioka, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

The influence of asymmetry in drop shape on an interfacial tension measurement

Y. Hayami, 1996 .

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

T. Miyashita, Y. Sambonsugi, T. Sugii, 2007, 2007 IEEE International Electron Devices Meeting.