Fu-Liang Yang

发表

9nm half-pitch functional resistive memory cell with <1µA programming current using thermally oxidized sub-stoichiometric WOx film

C. Hu, C. Ho, Cho-Lun Hsu, 2010, 2010 International Electron Devices Meeting.

Utilizing Sub-5 nm sidewall electrode technology for atomic-scale resistive memory fabrication

Y. J. Chen, C. C. Chen, C. H. Lin, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

25 nm CMOS Omega FETs

Y. Yeo, C. Hu, M. Liang, 2002, Digest. International Electron Devices Meeting,.

Novel 20nm hybrid SOI/bulk CMOS technology with 0.183/spl mu/m/sup 2/ 6T-SRAM cell by immersion lithography

Tsai-Sheng Gau, Jaw-Jung Shin, Chien-Chao Huang, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Discrete Dopant Fluctuations in 20-nm/15-nm-Gate Planar CMOS

Shao-Ming Yu, Fu-Liang Yang, Yiming Li, 2008, IEEE Transactions on Electron Devices.

Effect of Top Electrode Material on Resistive Switching Properties of $\hbox{ZrO}_{2}$ Film Memory Devices

C. Hu, Fu-Liang Yang, T. Tseng, 2007, IEEE Electron Device Letters.

BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design

C. Hu, A. Niknejad, W. Xiong, 2007, 2007 IEEE Symposium on VLSI Technology.

Heterogeneously integrated sub-40nm low-power epi-like Ge/Si monolithic 3D-IC with stacked SiGeC ambient light harvester

G. Huang, Meng-Fan Chang, Fu-Liang Yang, 2014, 2014 IEEE International Electron Devices Meeting.

Monolithic 3D chip integrated with 500ns NVM, 3ps logic circuits and SRAM

G. Huang, C. Hu, Meng-Fan Chang, 2013, 2013 IEEE International Electron Devices Meeting.

Fast programming metal-gate Si quantum dot nonvolatile memory using green nanosecond laser spike annealing

C. Hu, C. Pan, Fu-Liang Yang, 2012 .

Inductively coupled plasma grown semiconductor films for low cost solar cells with improved light-soaking stability

Jung Y. Huang, C. Pan, H. Kuo, 2011 .

Thin film silicon solar cell fabricated at 100°C by high density plasma for flexible photovoltaic application

Jung Y. Huang, H. Kuo, Fu-Liang Yang, 2010, CLEO/QELS: 2010 Laser Science to Photonic Applications.

A Novel Nanoinjection Lithography (NInL) Technology and Its Application for 16-nm Node Device Fabrication

C. Hu, Chun-Chi Chen, Jan-Tsai Liu, 2011, IEEE Transactions on Electron Devices.

3D 65nm CMOS with 320°C microwave dopant activation

J. M. Kowalski, Chia-Chen Wan, Yao-Jen Lee, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Hybrid Si/TMD 2D electronic double channels fabricated using solid CVD few-layer-MoS2 stacking for Vth matching and CMOS-compatible 3DFETs

Chenming Hu, Yi-Ju Chen, Lain-Jong Li, 2014, 2014 IEEE International Electron Devices Meeting.

Hot-Carrier-induced Degradation on 0.1μm Partially Depleted SOI CMOSFET with thin Oxide

W. Yeh, Fu-Liang Yang, Y. Fang, 2002 .

Modeling isolation-induced mechanical stress effect on SOI MOS devices

Ke-Wei Su, Di-Hong Lee, Chien-Chao Huang, 2003, 2003 IEEE International Conference on SOI.

Stable and near-omni-directional high-efficiency amorphous Si photovoltaic devices

Jung Y. Huang, C. Pan, H. Kuo, 2011, CLEO: 2011 - Laser Science to Photonic Applications.

Novel 140°C hybrid thin film solar cell/transistor technology with 9.6% conversion efficiency and 1.1 cm2/V-s electron mobility for low-temperature substrates

Jung Y. Huang, C. Hu, C. Pan, 2010, 2010 International Electron Devices Meeting.

The Implementation of Polysilicon Nanowire based Biomolecular Sensor System-on-Chip

S. Lu, C. Ho, Fu-Liang Yang, 2012 .

UV–Visible Light-Trapping Structure of Loosely Packed Submicrometer Silica Sphere for Amorphous Silicon Solar Cells

H. Kuo, Fu-Liang Yang, C. Shen, 2012, IEEE Electron Device Letters.

Potential application of thin-film nanotechnologies in third-generation Si solar cells

Fu-Liang Yang, C. Shen, J. Shieh, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

High performance 0.1 /spl mu/m PD SOI tunneling-biased MOSFETs (TBMOS)

C. Hu, Yu-Lin Chu, Kuo-Nan Yang, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

45nm node planar-SOI technology with 0.296μm2 6T-SRAM cell

Chenming Hu, Mong-Song Liang, Fu-Liang Yang, 2004, VLSIT 2004.

45nm Node Planar-SO1 Technology with 0.296pm2 6T-SUM Cell

Chenming Hu, Mong-Song Liang, Di-Hong Lee, 2004 .

Characterization and modeling of SOI varactors at various temperatures

Kun-Ming Chen, G. Huang, W. Yeh, 2004, Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442).

Hot-carrier-induced degradation for partially depleted SOI 0.25-0.1 /spl mu/m CMOSFET with 2-nm thin gate oxide

W. Yeh, Fu-Liang Yang, Y. Fang, 2002 .

Characteristic Fluctuation Dependence on Discrete Dopant for 16nm SOI FinFETs at Different Temperature

Yiming Li, Hui-Wen Cheng, Fu-Liang Yang, 2007 .

Exploratory study of Resistive Random Access Memory (R-RAM) scaling beyond 10nm

C. Ho, Fu-Liang Yang, 2013, 2012 12th Annual Non-Volatile Memory Technology Symposium Proceedings.

Low-Temperature Microwave Annealing Processes for Future IC Fabrication—A Review

Yao-Jen Lee, C. Hu, P. Sung, 2014, IEEE Transactions on Electron Devices.

Rapid (<5 min) Identification of Pathogen in Human Blood by Electrokinetic Concentration and Surface-Enhanced Raman Spectroscopy

C. Hu, Hsien-Chang Chang, Fu-Liang Yang, 2013, Scientific Reports.

An Assessment of Single-Electron Effects in Multiple-Gate SOI MOSFETs with 1.6-nm Gate Oxide near Room Temperature

P. Su, Fu-Liang Yang, Chang-Yun Chang, 2005, 2005 International Semiconductor Device Research Symposium.

35 nm CMOS FinFETs

Yang-Kyu Choi, Chenming Hu, Mong-Song Liang, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Sub-60mV-swing negative-capacitance FinFET without hysteresis

Chenming Hu, Sayeef Salahuddin, Kai-Shin Li, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Novel solar down-conversion luminescent and switchable interface polarization material by europium doped Si-O polar structures

C. Pan, H. Kuo, Fu-Liang Yang, 2012, 2012 Conference on Lasers and Electro-Optics (CLEO).

Random Telegraph Noise in 1X-nm CMOS Silicide Contacts and a Method to Extract Trap Density

G. Huang, C. Hu, Tahui Wang, 2012, IEEE Electron Device Letters.

Impact of post-deposition-annealing on the electrical characteristics of HfOxNy gate dielectric on Ge substrate

Chun-Yen Chang, Chien-Chao Huang, Fu-Liang Yang, 2005 .

Strained CMOS Devices With Shallow-Trench-Isolation Stress Buffer Layers

Shao-Ming Yu, Hung-Ming Chen, Fu-Liang Yang, 2008, IEEE Transactions on Electron Devices.

Magnetic-composite-modified polycrystalline silicon nanowire field-effect transistor for vascular endothelial growth factor detection and cancer diagnosis.

C. Ho, Chien-Chao Huang, Fu-Liang Yang, 2014, Analytical chemistry.

Discrete Dopant Fluctuated 20nm/15nm-Gate Planar CMOS

Shao-Ming Yu, Hung-Ming Chen, Fu-Liang Yang, 2007, 2007 IEEE Symposium on VLSI Technology.

Efficiency enhancement and polarization detection capability of photodiode by accumulating local electric field on the metal electrodes

C. Ho, Fu-Liang Yang, Y. Lai, 2010, 2010 International Electron Devices Meeting.

High mobility high on/off ratio C-V dispersion-free Ge n-MOSFETs and their strain response

C. Hu, G. Luo, Fu-Liang Yang, 2010, 2010 International Electron Devices Meeting.

Scalable fabrication of a complementary logic inverter based on MoS2 fin-shaped field effect transistors

Ming-Yang Li, Lain-Jong Li, Kai-Shin Li, 2019, Nanoscale Horizons.

Nearly defect-free Ge gate-all-around FETs on Si substrates

C. Hu, P. Sung, G. Luo, 2011, 2011 International Electron Devices Meeting.

A flexible, highly-sensitive, and easily-fabricated carbon-nanotubes tactile sensor on polymer substrate

Weileun Fang, ChiaHua Ho, Fu-Liang Yang, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

Vth adjustable self-aligned embedded source/drain Si/Ge nanowire FETs and dopant-free NVMs for 3D sequentially integrated circuit

Fu-Liang Yang, C. Shen, J. Shieh, 2014, 2014 IEEE International Electron Devices Meeting.

Triangular-channel Ge NFETs on Si with (111) sidewall-enhanced Ion and nearly defect-free channels

G. Huang, C. Hu, F. Hou, 2012, 2012 International Electron Devices Meeting.

5nm-gate nanowire FinFET

Chenming Hu, Yee-Chia Yeo, Mong-Song Liang, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Temperature dependence of hot-carrier-induced degradation in 0.1 μm SOI nMOSFETs with thin oxide

Fu-Liang Yang, Wen-Kuan Yeh, Wen-Han Wang, 2002 .

A numerical study of Si-TMD contact with n/p type operation and interface barrier reduction for sub-5 nm monolayer MoS2 FET

C. Hu, W. Yeh, Tahui Wang, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

MoS2 U-shape MOSFET with 10 nm channel length and poly-Si source/drain serving as seed for full wafer CVD MoS2 availability

Jia-Min Shieh, Yu-Lun Chueh, Chenming Hu, 2016, 2016 IEEE Symposium on VLSI Technology.

3D Ferroelectric-like NVM/CMOS hybrid chip by sub-400 °C sequential layered integration

C. Hu, C. Pan, Fu-Liang Yang, 2012, 2012 International Electron Devices Meeting.

Record-high 121/62 μA/μm on-currents 3D stacked epi-like Si FETs with and without metal back gate

Jia-Min Shieh, Kuei-Shu Chang-Liao, Ci-Ling Pan, 2013, 2013 IEEE International Electron Devices Meeting.

Nonvolatile memory with switching interfacial polar structures of nano Si-in-mesoporous silica

Jung Y. Huang, C. Pan, H. Kuo, 2009 .

TMD FinFET with 4 nm thin body and back gate control for future low power technology

Yao-Jen Lee, C. Hu, W. Yeh, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Full low temperature microwave processed Ge CMOS achieving diffusion-less junction and Ultrathin 7.5nm Ni mono-germanide

Yao-Jen Lee, C. Hu, P. Sung, 2012, 2012 International Electron Devices Meeting.

A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications

Chia-Hua Ho, Min-Cheng Chen, Hao-Yu Chen, 2012, Sensors.

A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin

Chenming Hu, ChiaHua Ho, Yi-Ping Hsieh, 2013, 2013 Symposium on VLSI Technology.

Strained FIP-SOI (finFET/FD/PD-SOI) for sub-65 nm CMOS scaling

J.Y.-C. Sun, Chenming Hu, Mong-Song Liang, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Low-cost and TSV-free monolithic 3D-IC with heterogeneous integration of logic, memory and sensor analogy circuitry for Internet of Things

Meng-Fan Chang, Guo-Wei Huang, Ting-Jen Hsueh, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).