B. Sano

Piranha: a scalable architecture based on single-chip multiprocessing

Luiz André Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions

Chia-Lin Yang, Barton Sano, Alvin R. Lebeck, 2000, IEEE Trans. Computers.

Exploiting instruction level parallelism in geometry processing for three dimensional graphics applications

Chia-Lin Yang, Barton Sano, Alvin R. Lebeck, 1998, Proceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture.

Design and Analysis of Hardware for High-Performance Prolog

Peter Van Roy, Alvin M. Despain, Barton Sano, 1996, J. Log. Program..

Fast Prolog with an extended general purpose architecture

Peter Van Roy, Alvin M. Despain, Barton Sano, 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.

The 16-fold way: a microparallel taxonomy

A. Despain, B. Sano, 1993, Proceedings of the 26th Annual International Symposium on Microarchitecture.