Juinn-Dar Huang

发表

Efficient Circuit Structure Analysis for Automatic Behavioral Model Generation in Mixed-Signal System Simulation

Jing-Yang Jou, Juinn-Dar Huang, Ling-Yen Song, 2021 .

A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication

Jing-Yang Jou, Juinn-Dar Huang, Chien-Hua Chen, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM

Jing-Yang Jou, Juinn-Dar Huang, Che-Hua Shih, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Concentration-Resilient Mixture Preparation with Digital Microfluidic Lab-on-Chip

Yi-Ling Chen, Bhargab B. Bhattacharya, Juinn-Dar Huang, 2018, ACM Trans. Embed. Comput. Syst..

An SoC Integration Ready VLIW-Driven CNN Accelerator with High Utilization and Scalability

Juinn-Dar Huang, Chia-Heng Hu, I-Hao Tseng, 2022, 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS).

A variable partitioning algorithm of BDD for FPGA technology mapping

Juinn-Dar Huang, Jie Hong Jiang, Jing Yang Jout, 1997 .

Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model

Chia-Cheng Wu, Juinn-Dar Huang, Chia-Chun Lin, 2021, ACM J. Emerg. Technol. Comput. Syst..

Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays

Chia-Cheng Wu, Chun-Yao Wang, Juinn-Dar Huang, 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Defect-aware synthesis for reconfigurable single-electron transistor arrays

Juinn-Dar Huang, Yi-Hang Chen, Jia-Shin Lu, 2017, 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

ROBDD-based area minimization synthesis for reconfigurable single-electron transistor arrays

Yang Chen, Juinn-Dar Huang, Yi-Hang Chen, 2015, VLSI Design, Automation and Test(VLSI-DAT).

Product Term Minimization in ROBDDs with Application to Reconfigurable SET Array Synthesis

Juinn-Dar Huang, Yi-Hang Chen, Yang-Wen Chen, 2015 .

Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints

Juinn-Dar Huang, Jian-Yu Chen, Yi-Hang Chen, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Coarse-Grained Dual-Convolver Based CNN Accelerator with High Computing Resource Utilization

Yi Lu, Juinn-Dar Huang, Yi-Lin Wu, 2020, 2020 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS).

Design Automation for Dilution of a Fluid Using Programmable Microfluidic Device--Based Biochips

Ankur Gupta, Sudip Roy, Juinn-Dar Huang, 2019, ACM Trans. Design Autom. Electr. Syst..

Reactant Minimization in Sample Preparation on Digital Microfluidic Biochips

Chia-Hung Liu, Ting-Wei Chiang, Juinn-Dar Huang, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Reactant and Waste Minimization in Multitarget Sample Preparation on Digital Microfluidic Biochips

Chia-Hung Liu, Juinn-Dar Huang, Huei-Shan Lin, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant Multiplication

Jing-Yang Jou, Bu-Ching Lin, Juinn-Dar Huang, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping

Jing-Yang Jou, Wen-Zen Shen, Juinn-Dar Huang, 1996, Proceedings of International Conference on Computer Aided Design.

FSM-based transaction-level functional coverage for interface compliance verification

Jing-Yang Jou, Juinn-Dar Huang, Che-Hua Shih, 2006, Asia and South Pacific Conference on Design Automation, 2006..

FSM-Based Formal Compliance Verification of Interface Protocols

Chia-Chih Yen, Jing-Yang Jou, Juinn-Dar Huang, 2010, J. Inf. Sci. Eng..

ENHANCEMENT OF HEAT TRANSFER OF MIXING CONVECTION IN A VERTICAL CHANNEL BY A MOVING BLOCK

Juinn-Dar Huang, Yun K Huang, W. Fu, 2013 .

Throughput-driven hierarchical placement for two-dimensional regular multicycle communication architecture

Juinn-Dar Huang, Ya-Shih Huang, Juinn-Dar Huang, 2010, 2nd Asia Symposium on Quality Electronic Design (ASQED).

Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture

Yen-Ting Lin, Juinn-Dar Huang, Chia-I Chen, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Unified functional decomposition via encoding for FPGA technology mapping

Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Compatible class encoding in hyper-function decomposition for FPGA synthesis

Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Latency-optimization synthesis with module selection for digital microfluidic biochips

Chia-Hung Liu, Juinn-Dar Huang, Kuang-Cheng Liu, 2013, 2013 IEEE International SOC Conference.

Dilution and Mixing Algorithms for Flow-Based Microfluidic Biochips

Sudip Roy, Bhargab B. Bhattacharya, Juinn-Dar Huang, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Reactant Minimization for Multi-Target Sample Preparation on Digital Microfluidic Biochips Using Network Flow Models

Juinn-Dar Huang, Kang-Yi Fan, Shigeru Yamashita, 2019, 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Graph-based optimal reactant minimization for sample preparation on digital microfluidic biochips

Chia-Hung Liu, Ting-Wei Chiang, Juinn-Dar Huang, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

Reactant minimization during sample preparation on digital microfluidic biochips using skewed mixing trees

Chia-Hung Liu, Ting-Wei Chiang, Juinn-Dar Huang, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

An Efficient and Low-Power MLP Accelerator Architecture Supporting Structured Pruning, Sparse Activations and Asymmetric Quantization for Edge Computing

Juinn-Dar Huang, Ya-Chu Chang, Wei-Chen Lin, 2021, 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS).

Reducing fault dictionary size for million-gate large circuits

Juinn-Dar Huang, Yu-Ru Hong, Juinn-Dar Huang, 2009, TODE.

Fault Dictionary Size Reduction for Million-Gate Large Circuits

Juinn-Dar Huang, Yu-Ru Hong, Juinn-Dar Huang, 2007, 2007 Asia and South Pacific Design Automation Conference.

A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses

Jing-Yang Jou, Bu-Ching Lin, Juinn-Dar Huang, 2007, 2007 Asia and South Pacific Design Automation Conference.

Low power multiplexer tree design using dynamic propagation path control

Juinn-Dar Huang, Han-Jung Huang, Nan-Shing Li, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

Configurable Multi-Precision Floating-Point Multiplier Architecture Design for Computation in Deep Learning

Juinn-Dar Huang, Yu-Hsiang Huang, Pei-Hsuan Kuo, 2023, 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS).

High-performance NAND flash controller exploiting parallel out-of-order command execution

Juinn-Dar Huang, Yu-Hsiang Kao, Juinn-Dar Huang, 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.

Microarchitecture-Aware Floorplanning for Processor Performance Optimization

Hung-Ming Chen, Juinn-Dar Huang, Chi-Ying Chen, 2007, 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication

Juinn-Dar Huang, Chia-I Chen, Juinn-Dar Huang, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Performance-driven architectural synthesis for distributed register-file microarchitecture considering inter-island delay

Jing-Yang Jou, Juinn-Dar Huang, Chia-I Chen, 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.

TherWare: Thermal-Aware Placement and Routing Framework for 3D FPGAs with Location-Based Heat Balance

Juinn-Dar Huang, Ya-Shih Huang, Han-Yuan Chang, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Throughput optimization for latency-insensitive system with minimal queue insertion

Juinn-Dar Huang, Yi-Hang Chen, Ya-Chien Ho, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Two-staged parallel layer-aware partitioning for 3D designs

Yi-Ting Chen, Juinn-Dar Huang, Yi-Hang Chen, 2014, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test.

Thermal-aware logic block placement for 3D FPGAs considering lateral heat dissipation (abstract only)

Juinn-Dar Huang, Ya-Shih Huang, Han-Yuan Chang, 2012, FPGA '12.

Layer-Aware Design Partitioning for Vertical Interconnect Minimization

Juinn-Dar Huang, Ya-Shih Huang, Yang-Hsiang Liu, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

Architectural exploration of 3D FPGAs towards a better balance between area and delay

Juinn-Dar Huang, Chia-I Chen, Bau-Cheng Lee, 2011, 2011 Design, Automation & Test in Europe.

Equivalence checking of scheduling with speculative code transformations in high-level synthesis

Jing-Yang Jou, Juinn-Dar Huang, Che-Hua Shih, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

CriAS: A performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture

Juinn-Dar Huang, Chia-I Chen, Juinn-Dar Huang, 2009, 2009 Asia and South Pacific Design Automation Conference.