C. Nicopoulos

发表

Performance and power optimization through data compression in Network-on-Chip architectures

Chita R. Das, Narayanan Vijaykrishnan, Reetuparna Das, 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension

C. Nicopoulos, Karyofyllis Patsidis, Dimitris Konstantinou, 2018, Microprocess. Microsystems.

HoPE: Hot-Cacheline Prediction for Dynamic Early Decompression in Compressed LLCs

Hyung Gyu Lee, C. Nicopoulos, Vinson Young, 2017, ACM Trans. Design Autom. Electr. Syst..

Templatized Fused Vector Floating-Point Dot Product for High-Level Synthesis

C. Nicopoulos, G. Dimitrakopoulos, Dionysios Filippas, 2022, Journal of Low Power Electronics and Applications.

LeapConv: An Energy-Efficient Streaming Convolution Engine with Reconfigurable Stride

C. Nicopoulos, G. Dimitrakopoulos, Dionysios Filippas, 2022, 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

A dual-phase compression mechanism for hybrid DRAM/PCM main memory architectures

Jongman Kim, Chrysostomos Nicopoulos, Hyung Gyu Lee, 2012, GLSVLSI '12.

An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems

Jongman Kim, Chrysostomos Nicopoulos, Hyung Gyu Lee, 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

Low-Cost Online Convolution Checksum Checker

N. Mitianoudis, C. Nicopoulos, G. Dimitrakopoulos, 2022, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Large-Scale Semantic Concept Detection on Manycore Platforms for Multimedia Mining

Jongman Kim, Chrysostomos Nicopoulos, Mamadou Diao, 2011, 2011 IEEE International Parallel & Distributed Processing Symposium.

Do we need wide flits in Networks-on-Chip?

Jongman Kim, Junghee Lee, Chrysostomos Nicopoulos, 2013, 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

A High-Performance and Energy-Efficient Virtually Tagged Stack Cache Architecture for Multi-core Environments

Jongman Kim, Chrysostomos Nicopoulos, Hyung Gyu Lee, 2011, 2011 IEEE International Conference on High Performance Computing and Communications.

An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Yiannakis Sazeides, 2016, ACM Trans. Archit. Code Optim..

Timing-Driven Placement Optimization Facilitated by Timing-Compatibility Flip-Flop Clustering

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Ioannis Seitanidis, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Design Space Exploration Framework for ANN-Based Fault Detection in Hardware Systems

Theocharis Theocharides, Chrysostomos Nicopoulos, Andreas G. Savva, 2017, J. Electr. Comput. Eng..

HARPA: Solutions for dependable performance under physically induced performance variability

Francky Catthoor, Dimitrios Soudris, Chrysostomos Nicopoulos, 2015, 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS).

An Exploration of Hardware Architectures for Face Detection

Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides, 2006 .

Optimizing Data-Center TCO with Scale-Out Processors

Babak Falsafi, Yiannakis Sazeides, Damien Hardy, 2012, IEEE Micro.

ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers

Chita R. Das, Narayanan Vijaykrishnan, Jongman Kim, 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

Virtualizing Virtual Channels for Increased Network-on-Chip Robustness and Upgradeability

Jongman Kim, Chrysostomos Nicopoulos, Vassos Soteriou, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

Multi-Armed Bandits for Autonomous Timing-driven Design Optimization

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Apostolos Stefanidis, 2019, 2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS).

Thermal characterization of cloud workloads on a power-efficient server-on-chip

Yiannakis Sazeides, Djordje Jevdjic, Dragomir Milojevic, 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

A novel dimensionally-decomposed router for on-chip communication in 3D architectures

Chita R. Das, Narayanan Vijaykrishnan, Reetuparna Das, 2007, ISCA '07.

On the Effects of Process Variation in Network-on-Chip Architectures

Chita R. Das, Narayanan Vijaykrishnan, Mary Jane Irwin, 2010, IEEE Transactions on Dependable and Secure Computing.

On the Effects of Process Variation

Chita R. Das, Mary Jane Irwin, Aditya Yanamandra, 2010 .

ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Ioannis Seitanidis, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers

Chrysostomos Nicopoulos, William Fornaciari, Yiannakis Sazeides, 2017, J. Parallel Distributed Comput..

Switch folding: Network-on-Chip routers with time-multiplexed output ports

Emmanouil Kalligeros, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks

Chita R. Das, Narayanan Vijaykrishnan, Jongman Kim, 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

ShortPath: A Network-on-Chip Router with Fine-Grained Pipeline Bypassing

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Ioannis Seitanidis, 2016, IEEE Transactions on Computers.

ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39]

Chita R. Das, Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, 2009 .

Thermal Characterization of Cloud Workloads on a Low-power Server-on-Chip

B. Falsafi, A. Prodromou, D. Hardy, 2012 .

Toward Multi-Layer Holistic Evaluation of System Designs

Chrysostomos Nicopoulos, Yiannakis Sazeides, Emre Özer, 2016, IEEE Computer Architecture Letters.

Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43]

Chita R. Das, Vijaykrishnan Narayanan, Chrysostomos Nicopoulos, 2009 .

Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based Optimization

Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos, Apostolos Stefanidis, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs

Paolo Ienne, Philip Brisk, Alessandro Cevrero, 2009, TRETS.

Design space exploration for field programmable compressor trees

Paolo Ienne, Philip Brisk, Alessandro Cevrero, 2008, CASES '08.

A Low-Latency Power-Efﬁcient Convolutional Neural Network Accelerator for Vision Processing Algorithms

C. Nicopoulos, Junghee Lee, Max Pooling, 2020 .

A Convolutional Neural Network Accelerator for Power-Efﬁcient Real-Time Vision Processing

C. Nicopoulos, Junghee Lee, Max Pooling, 2019 .

CENICS 2019

C. Travieso-González, D. Stroobandt, C. Nicopoulos, 2019 .

Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Yiannakis Sazeides, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15]

Chita R. Das, Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, 2009 .