D. Kelly

A 16b /spl Sigma//spl Delta/ pipeline ADC with 2.5 MHz output data-rate

T. Brooks, D. Robertson, D. Kelly, 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz

M. Timko, L. Singer, D. Kelly, 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

Cascaded sigma-delta pipelien A/D converter with 1.25 MHz signal bandwidth and 89 DB SNR

David H. Robertson, T. Brooks, D. Robertson, 1999 .

A dual channel IF-digitizing IC with 117dB dynamic range at 300Mhz IF for EDGE/GSM base-stations [receiver]

Michael Elliott, Greg Patterson, Frank Murden, 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology

Gabriele Manganaro, Phil Brown, Janet Brunsilius, 2017, IEEE Journal of Solid-State Circuits.

A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC

S. Devarajan, L. Singer, D. Kelly, 2009, IEEE Journal of Solid-State Circuits.

A 16b 125MS/s 385mW 78.7dB SNR CMOS pipeline ADC

Paul Wilkins, Abhishek Kamath, Larry Singer, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input

Wenhua Yang, Lawrence A. Singer, Daniel F. Kelly, 2001, IEEE J. Solid State Circuits.