O. Schliebusch

A universal technique for fast and flexible instruction-set architecture simulation

G. Braun, A. Nohl, R. Leupers, 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

A NEW ENTRY POINT FOR ASIP IMPLEMENTATION

Rainer Leupers, Heinrich Meyr, Oliver Schliebusch, 2007 .

CONFIGURABLE PROCESSOR FEATURES

Rainer Leupers, Heinrich Meyr, Oliver Schliebusch, 2007 .

RTL processor synthesis for architecture exploration and implementation

Rainer Leupers, Gerd Ascheid, Heinrich Meyr, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Instruction encoding synthesis for architecture exploration using hierarchical processor models

Rainer Leupers, Heinrich Meyr, Andreas Hoffmann, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

A universal technique for fast and flexible instruction-set architecture simulation

Rainer Leupers, Heinrich Meyr, Andreas Hoffmann, 2002, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A framework for automated and optimized ASIP implementation supporting multiple hardware description languages

H. Meyr, G. Ascheid, R. Leupers, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

["Lean management" in hospitals: potentials and limitations].

O. Schliebusch, J. Glossmann, R. Walshe, 2000, Medizinische Klinik.