K. Adachi

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and ni SALICIDE

T. Kudo, H. Ishiuchi, M. Takayanagi, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

14 nm gate length CMOSFETs utilizing low thermal budget process with poly-SiGe and Ni salicide

Y. Toyoshima, K. Ohuchi, H. Yoshimura, 2002, Digest. International Electron Devices Meeting,.

S/D Engineering for Sub-100 nm MOSFET using Ultra Shallow Junction Formation Technique, Elevated S/D Structure and SALICIDE Technique

Y. Toyoshima, A. Hokazono, K. Adachi, 2002 .

Development of novel fabrication techniques for a silicon micro-vertex detector unit using the Flip-Chip bonding method

D. Tatsumi, C. Fukunaga, T. Kawasaki, 1994 .

High channel mobility in normally-off 4H-SiC buried channel MOSFETs

K. Adachi, K. Fukuda, S. Harada, 2001, IEEE Electron Device Letters.

8.5 m/spl Omega/ /spl middot/ cm/sub 2/ 600-V double-epitaxial MOSFETs in 4H-SiC

K. Adachi, K. Fukuda, T. Yatsuo, 2004, IEEE Electron Device Letters.

Experimental Extraction of Body Bias Dependence of Low Frequency Noise in sub-micron MOSFETs from Subthreshold to Moderate Inversion Regime

K. Adachi, C. Tanaka, S. Yoshitomi, 2019, 2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS).

Optimized halo structure for 80 nm physical gate CMOS technology with indium and antimony highly angled ion implantation

M. Takayanagi, Y. Toyoshima, M. Fujiwara, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

An ultra-low R/sub ons/ in 4H-SiC vertical MOSFET: buried channel double-epitaxial MOSFET

K. Adachi, K. Arai, S. Harada, 2004, 2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs.

Ultra Low Voltage Operations in Bulk CMOS Logic Circuits with Dopant Segregated Schottky Source/Drain Transistors

J. Koga, Y. Toyoshima, F. Matsuoka, 2006, 2006 International Electron Devices Meeting.