A. Azuma

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and ni SALICIDE

T. Kudo, H. Ishiuchi, M. Takayanagi, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Integration technology of polymetal (W/WSiN/Poly-Si) dual gate CMOS for 1 Gbit DRAMs and beyond

Y. Akasaka, Y. Toyoshima, K. Nakajima, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Hf layer thickness dependence of resistive switching characteristics of Ti/Hf/HfO2/Au resistive random access memory device

T. Shimizu, S. Shingubara, A. Azuma, 2018 .

Performance improvement of metal gate CMOS technologies

Y. Toyoshima, S. Matsuda, A. Azuma, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

Threshold switching of a NbOx device prepared by DC reactive sputtering

T. Shimizu, S. Shingubara, A. Azuma, 2019, Japanese Journal of Applied Physics.

Direct measurement and analysis of highly injected intrinsic base potential

A. Azuma, H. Momose, T. Maeda, 1991, Proceedings of the 1991 Bipolar Circuits and Technology Meeting.

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

D. Mocuta, C. Norris, C. Radens, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Novel High-Performance Analog Devices for Advanced Low-Power High-k Metal Gate Complementary Metal–Oxide–Semiconductor Technology

F. S. Johnson, R. Wachnik, K. Barla, 2011 .