Xin Si

发表

A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors

Meng-Fan Chang, Yen-Cheng Chiu, Wei-Chen Wei, 2020, IEEE Journal of Solid-State Circuits.

1 Conv-RAM : An Energy-Efficient SRAM with Embedded Convolution Computation for Low-Power CNN-Based Machine Learning Applications

Shimeng Yu, Meng-Fan Chang, Qiang Li, 2018 .

Design Methodology and Trends of SRAM-Based Compute-in-Memory Circuits

Meng-Fan Chang, Xin Si, Fangyuan Dong, 2022, 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT).

A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors

Meng-Fan Chang, Qiang Li, Xin Si, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors

Meng-Fan Chang, Shimeng Yu, Rui Liu, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

Evaluation Platform of Time-Domain Computing-in-Memory Circuits

X. Chen, Jun Yang, Xin Si, 2023, IEEE Transactions on Circuits and Systems II: Express Briefs.

VCCIM: a voltage coupling based computing-in-memory architecture in 28 nm for edge AI applications

X. Chen, Xin Si, Chen Xue, 2022, CCF Transactions on High Performance Computing.

A computing-in-memory macro based on three-dimensional resistive random-access memory

Ming Liu, Meng-Fan Chang, Xin Si, 2022, Nature Electronics.

A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors

Meng-Fan Chang, Xiaoyu Sun, Shimeng Yu, 2020, IEEE Journal of Solid-State Circuits.

Design Challenges and Methodology of High-Performance SRAM-Based Compute-in-Memory for AI Edge Devices

Xin Si, Yufei Wang, Yongliang Zhou, 2021, 2021 International Conference on UK-China Emerging Technologies (UCET).

Challenge and Trend of SRAM Based Computation-in-Memory Circuits for AI Edge Devices

Jun Yang, Meng-Fan Chang, Xin Si, 2021, 2021 IEEE 14th International Conference on ASIC (ASICON).

Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices

Jun Yang, Xin Si, Chen Xue, 2021, 2021 18th International SoC Design Conference (ISOCC).

15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization

Xin Si, Shouyi Yin, Shaojun Wei, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips

Meng-Fan Chang, Qiang Li, Tzu-Hsiang Hsu, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips

Shih-Chieh Chang, Meng-Fan Chang, Shanshi Huang, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors

Meng-Fan Chang, Yen-Cheng Chiu, Wei-Chen Wei, 2019, 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Circuit Design Challenges in Computing-in-Memory for AI Edge Devices

Meng-Fan Chang, Heng-Yuan Lee, Huaqiang Wu, 2019, 2019 IEEE 13th International Conference on ASIC (ASICON).

24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning

Meng-Fan Chang, Shimeng Yu, Yen-Cheng Chiu, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

MLFlash-CIM: Embedded Multi-Level NOR-Flash Cell based Computing in Memory Architecture for Edge AI Devices

Xin Si, Qiang Li, Chunmeng Dou, 2021, 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS).

A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips

Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, 2021, IEEE Journal of Solid-State Circuits.

A computing-in-memory macro based on three-dimensional resistive random-access memory

Meilin Liu, Meng-Fan Chang, Xin Si, 2022, Nature Electronics.

A Booth-based Digital Compute-in-Memory Marco for Processing Transformer Model

Xin Si, An Guo, Bo Wang, 2022, 2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

33.4 A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference

Jun Yang, Xin Si, Yanan Guo, 2023, 2023 IEEE International Solid- State Circuits Conference (ISSCC).

14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse

Meng-Fan Chang, Xueqing Li, Huazhong Yang, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization

Ruiqi Guo, Meng-Fan Chang, Xin Si, 2023, IEEE Journal of Solid-State Circuits.

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control

Qi Liu, Xin Si, Yongpan Liu, 2021, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 40nm 1Mb 35.6 TOPS/W MLC NOR-Flash Based Computation-in-Memory Structure for Machine Learning

Xin Si, Jingjing Li, Qiang Li, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

Parallelizing SRAM Arrays with Customized Bit-Cell for Binary Neural Networks

Meng-Fan Chang, Xiaochen Peng, Shimeng Yu, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks

Jun Yang, Xin Si, Chen Xue, 2023, IEEE International Solid-State Circuits Conference.

A Charge-Digital Hybrid Compute-In-Memory Macro with full precision 8-bit Multiply-Accumulation for Edge Computing Devices

Xin Si, Tianzhu Xiong, Jinwu Chen, 2022, International Symposium on Embedded Multicore/Many-core Systems-on-Chip.

A Half-Select Disturb-Free 11T SRAM Cell With Built-In Write/Read-Assist Scheme for Ultralow-Voltage Operations

Xin Si, Bo Zhang, Shaowei Zhen, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs

X. Chen, Jun Yang, Xin Si, 2023, IEEE International Solid-State Circuits Conference.

Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips

Xin Si, Shyh-Shyuan Sheu, Ting-Wei Chang, 2022, IEEE Journal of Solid-State Circuits.

STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse

Huazhong Yang, Meilin Liu, Yongpan Liu, 2022, IEEE Journal of Solid-State Circuits.

A 14nm 100Kb 2T1R Transpose RRAM with >150X resistance ratio enhancement and 27.95% reduction on energy-latency product using low-power near threshold read operation and fast data-line current stabling scheme

Qi Liu, Ming Liu, H. Lv, 2021, Symposium on VLSI Technology.

Parallelizing SRAM Arrays with Customized Bit-Cell for Binary Neural Networks

Meng-Fan Chang, Xiaochen Peng, Shimeng Yu, 2018, Design Automation Conference.

ShareFloat CIM: A Compute-In-Memory Architecture with Floating-Point Multiply-and-Accumulate Operations

Jun Yang, Xin Si, Chen Xue, 2022, 2022 IEEE International Symposium on Circuits and Systems (ISCAS).

A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips

C. Lo, W. Lo, Meng-Fan Chang, 2023, IEEE Journal of Solid-State Circuits.