S. Sheu

发表

A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors

Meng-Fan Chang, Yen-Cheng Chiu, Wei-Chen Wei, 2020, IEEE Journal of Solid-State Circuits.

Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity

Frederick T. Chen, H. Y. Lee, Y. S. Chen, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Challenges and opportunities for HfOX based resistive random access memory

Frederick T. Chen, H. Y. Lee, Y. S. Chen, 2011, 2011 International Electron Devices Meeting.

Ultra-thin Hf0.5Zr0.5O2 Ferroelectric Tunnel Junction with High Current Density

P. Tzeng, T. Hou, W. Lo, 2021, 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Resistance instabilities in a filament-based resistive memory

Heng-Yuan Lee, Pang-Shiu Chen, Ming-Jinn Tsai, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Designs of emerging memory based non-volatile TCAM for Internet-of-Things (IoT) and big-data processing: A 5T2R universal cell

Mary Jane Irwin, Jack Sampson, Hsiang-Yun Cheng, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

RRAM-based 7T1R nonvolatile SRAM with 2x reduction in store energy and 94x reduction in restore energy for frequent-off instant-on applications

T. Ku, Albert Lee, C. Lin, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Process-Induced Magnetic Tunnel Junction Damage and its Recovery for the Development of Spin-Orbit Torque Magnetic Random Access Memory

W. Lo, Y. Hsin, S. Sheu, 2022, SSRN Electronic Journal.

Evidence and solution of over-RESET problem for HfOX based resistive memory with sub-ns switching speed and high endurance

Frederick T. Chen, W. H. Liu, H. Y. Lee, 2010, 2010 International Electron Devices Meeting.

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips

Shih-Chieh Chang, Meng-Fan Chang, Shanshi Huang, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors

Meng-Fan Chang, Yen-Cheng Chiu, Wei-Chen Wei, 2019, 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Circuit Design Challenges in Computing-in-Memory for AI Edge Devices

Meng-Fan Chang, Heng-Yuan Lee, Huaqiang Wu, 2019, 2019 IEEE 13th International Conference on ASIC (ASICON).

A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices

C. Lo, W. Lo, Meng-Fan Chang, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

RRAM Defect Modeling and Failure Analysis Based on March Test and a Novel Squeeze-Search Scheme

Frederick T. Chen, Cheng-Wen Wu, Ching-Yi Chen, 2015, IEEE Transactions on Computers.

Size-Dependent Switching Properties of Spin-Orbit Torque MRAM With Manufacturing-Friendly 8-Inch Wafer-Level Uniformity

Tuo-Hung Hou, Shyh-Shyuan Sheu, Chih-I Wu, 2020, IEEE Journal of the Electron Devices Society.

Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications

Meng-Fan Chang, Ming-Jinn Tsai, Che-Wei Wu, 2012, IEEE Journal of Solid-State Circuits.

Three-dimensional 4F2 ReRAM cell with CMOS logic compatible process

Meng-Fan Chang, Heng-Yuan Lee, Yu-Sheng Chen, 2010, 2010 International Electron Devices Meeting.

BEOL-Compatible Multiple Metal-Ferroelectric-Metal (m-MFM) FETs Designed for Low Voltage (2.5 V), High Density, and Excellent Reliability

P. Tzeng, T. Hou, W. Lo, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time

Meng-Fan Chang, Tien-Fu Chen, Heng-Yuan Lee, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing

Meng-Fan Chang, Tien-Fu Chen, Frederick T. Chen, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

RRAM-based Spiking Nonvolatile Computing-In-Memory Processing Engine with Precision-Configurable In Situ Nonlinear Activation

Yiran Chen, Meng-Fan Chang, Wei-Hao Chen, 2019, 2019 Symposium on VLSI Technology.

High-K metal gate contact RRAM (CRRAM) in pure 28nm CMOS logic process

Ming-Jinn Tsai, Ya-Chin King, Shyh-Shyuan Sheu, 2012, 2012 International Electron Devices Meeting.

A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes

Meng-Fan Chang, Heng-Yuan Lee, Yu-Sheng Chen, 2013, IEEE Journal of Solid-State Circuits.

Endurance-aware circuit designs of nonvolatile logic and nonvolatile sram using resistive memory (memristor) device

Meng-Fan Chang, Hiroyuki Yamauchi, Shyh-Shyuan Sheu, 2012, 17th Asia and South Pacific Design Automation Conference.

Resistance switching for RRAM applications

Heng-Yuan Lee, Yu-Sheng Chen, Pang-Shiu Chen, 2011, Science China Information Sciences.

Memory access algorithm for low energy CPU/GPU heterogeneous systems with hybrid DRAM/NVM memory architecture

Ming-Jinn Tsai, Lih-Yih Chiou, Pei-Hua Wang, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Three-Dimensional $\hbox{4F}^{2}$ ReRAM With Vertical BJT Driver by CMOS Logic Compatible Process

Heng-Yuan Lee, Ming-Jinn Tsai, Ya-Chin King, 2011, IEEE Transactions on Electron Devices.

Training-based forming process for RRAM yield improvement

Cheng-Wen Wu, Ching-Yi Chen, Shyh-Shyuan Sheu, 2011, 29th VLSI Test Symposium.

Modeling Fatigue-Breakdown Dilemma in Ferroelectric Hf0.5 Zr0.5 O2 and optimized Programming Strategies

I-Ting Wang, T. Hou, S. Sheu, 2022, 2022 International Electron Devices Meeting (IEDM).

3D Scalable, Wake-up Free, and Highly Reliable FRAM Technology with Stress-Engineered HfZrOx

M. H. Lee, S. S. Sheu, H. Y. Lee, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge

Heng-Yuan Lee, Ming-Hung Wu, Chih-Cheng Chang, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Fully 3-D symmetrical TSV monolithic transformer for RFIC

Shawn S. H. Hsu, S. S. Sheu, C. S. Lin, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices

C. Lo, W. Lo, Meng-Fan Chang, 2023, 2023 IEEE International Solid- State Circuits Conference (ISSCC).

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

A 16Mb dual-mode ReRAM macro with sub-14ns computing-in-memory and memory functions enabled by self-write termination scheme

Meng-Fan Chang, Yuan Xie, Heng-Yuan Lee, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Development of Highly Manufacturable, Reliable, and Energy-Efficient Spin-Orbit Torque Magnetic Random Access Memory (SOT-MRAM)

S. Z. Rahaman, Y. See, Y. Hsin, 2022, 2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Highly Reliable, Scalable, and High-Yield HfZrOx FRAM by Barrier Layer Engineering and Post-Metal Annealing

T. Hou, W. Lo, S. Sheu, 2022, 2022 International Electron Devices Meeting (IEDM).

An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology

W. Lo, Kuan-Neng Chen, Shih-Hsien Wu, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

Heng-Yuan Lee, Frederick T. Chen, Ming-Jinn Tsai, 2011, 2011 IEEE International Solid-State Circuits Conference.

Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips

Xin Si, Shyh-Shyuan Sheu, Ting-Wei Chang, 2022, IEEE Journal of Solid-State Circuits.

A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application

Shyh-Shyuan Sheu, Kuan-Neng Chen, Yao-Jen Chang, 2012, IEEE Transactions on Device and Materials Reliability.

Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300mm Multi-Project Wafer (MPW)

Sheng-Tsai Wu, John H. Lau, T.-H. Chen, 2011 .

A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing

Meng-Fan Chang, Tien-Fu Chen, Shyh-Shyuan Sheu, 2017, IEEE Journal of Solid-State Circuits.

A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing

Meng-Fan Chang, Tien-Fu Chen, Li-Yue Huang, 2016, IEEE Journal of Solid-State Circuits.

A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme

Heng-Yuan Lee, Yu-Sheng Chen, Pang-Shiu Chen, 2009, 2009 Symposium on VLSI Circuits.

Stray field and combined effects on device miniaturization of the magnetic tunnel junctions

Y. Hsin, S. Sheu, Chih-I Wu, 2022, Journal of Physics D: Applied Physics.

Structure and Performance Co-optimization for the Development of Highly Reliable Spin-Orbit Torque Magnetic Random Access Memory

S. Z. Rahaman, W. Lo, Y. Hsin, 2023, 2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT).

Electrical characterization of through silicon vias (TSVs) with an on chip bus driver for 3D IC integration

J. H. Lau, M. J. Kao, S. S. Sheu, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Electrical testing of blind Through-Silicon Via (TSV) for 3D IC integration

P. Tzeng, M. Kao, W. Lo, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Electrical Performance of Through-Silicon Vias (TSVs) for High-Frequency 3D IC Integration Applications

John H. Lau, Ming-Jer Kao, Shyh-Shyuan Sheu, 2012 .

Mixed etching-oxidation process to enhance the performance of spin-transfer torque MRAM for high-performance computing

Y. Hsin, S. Sheu, Shan-Yi Yang, 2024, Applied Physics Letters.

An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips

C. Lo, C. Hsieh, K. Tang, 2024, IEEE Journal of Solid-State Circuits.

A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips

C. Lo, C. Hsieh, K. Tang, 2024, IEEE Journal of Solid-State Circuits.

A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips

C. Lo, W. Lo, Meng-Fan Chang, 2023, IEEE Journal of Solid-State Circuits.