Y. Chan

A transregional CMOS SRAM with single, logic V/sub DD/ and dynamic power rails

S. Kosonocky, A. Bhavnagarwala, R. Joshi, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

A Sub-600mV, Fluctuation tolerant 65nm CMOS SRAM Array with Dynamic Cell Biasing

S. Kosonocky, Yuen Chan, K. Stawiasz, 2007, 2007 IEEE Symposium on VLSI Circuits.

High performance CMOS circuit techniques for the G-4 S/390 microprocessor

James D. Warnock, Yuen H. Chan, Leon J. Sigal, 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

Statistical Exploration of the Dual Supply Voltage Space of a 65nm PD/SOI CMOS SRAM Cell

Rouwaida Kanj, Ching-Te Chuang, Rajiv Joshi, 2006, 2006 European Solid-State Device Research Conference.

Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor

Ching-Te Chuang, William V. Huott, James D. Warnock, 1997, IBM J. Res. Dev..

Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics

Rajiv V. Joshi, Yue Tan, Ching-Te Chuang, 2009, IEEE Journal of Solid-State Circuits.

An advanced optical diagnostic technique of IBM z990 eServer microprocessor

Franco Stellari, Alan J. Weger, Peilin Song, 2005, IEEE International Conference on Test, 2005..

A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing

C. Radens, S.P. Kowalczyk, Yuen Chan, 2008, IEEE Journal of Solid-State Circuits.