U. Srinivasan

A transregional CMOS SRAM with single, logic V/sub DD/ and dynamic power rails

S. Kosonocky, A. Bhavnagarwala, R. Joshi, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

A Sub-600mV, Fluctuation tolerant 65nm CMOS SRAM Array with Dynamic Cell Biasing

S. Kosonocky, Yuen Chan, K. Stawiasz, 2007, 2007 IEEE Symposium on VLSI Circuits.

24.1 A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology

Rajiv V. Joshi, Daniel Friedman, Uma Srinivasan, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

An advanced optical diagnostic technique of IBM z990 eServer microprocessor

Franco Stellari, Alan J. Weger, Peilin Song, 2005, IEEE International Conference on Test, 2005..

A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing

C. Radens, S.P. Kowalczyk, Yuen Chan, 2008, IEEE Journal of Solid-State Circuits.