Marcelo de Oliveira Johann

发表

Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation

Guilherme Flach, Tiago Reimann, Gracieli Posser, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Designing a Mask Programmable Matrix for Sequential Circuits

Luigi Carro, Marcelo de Oliveira Johann, José Luís Almada Güntzel, 1999, VLSI.

On the accuracy of Elmore-based Delay Models

Tiago Reimann, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis, 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

Interaction Aesthetics and Ubiquitous Music

Marcelo de Oliveira Johann, Marcelo Soares Pimenta, Leandro Lesqueves Costalonga, 2015, Creativity in the Digital Age.

A study on the performance of fast initial placement algorithms

Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis, Renato Fernandes Hentschke, 2003, VLSI-SOC.

An analytical timing-driven algorithm for detailed placement

Guilherme Flach, Marcelo de Oliveira Johann, José Luís Almada Güntzel, 2015, 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS).

Relational Properties in Interaction Aesthetics: The Ubiquitous Music Turn

Marcelo de Oliveira Johann, Marcelo Soares Pimenta, Leandro Lesqueves Costalonga, 2014, EVA.

Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing

Guilherme Flach, Tiago Reimann, Gracieli Posser, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Testes e desenvolvimento de rotinas para roteamento de circuitos VLSI

Marcelo de Oliveira Johann, Claudia Dornelles Schneider, 1994 .

Quadratic placement with single-iteration linear system solver

Guilherme Flach, Marcelo de Oliveira Johann, Ricardo Reis, 2011, SBCCI '11.

Channel based routing in channel-less circuits

Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis, Glauco Borges Valim dos Santos, 2006, ISCAS.

A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits

Marcelo de Oliveira Johann, Ricardo Reis, Renato Fernandes Hentschke, 2006, VLSI-SoC.

Routing-Aware Incremental Timing-Driven Placement

Mateus Fogaça, Andrew A. Kennings, Guilherme Flach, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Improving placement algorithms by using visualization tools

Mateus Fogaça, Guilherme Flach, Marcelo de Oliveira Johann, 2016, 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS).

Ecologically grounded multimodal design: The Palafito 1.0 study

Marcelo de Oliveira Johann, Marcelo Soares Pimenta, Joseph Timoney, 2014, ICMC.

Drive Strength Aware Cell Movement Techniques for Timing Driven Placement

Mateus Fogaça, Guilherme Flach, Marcelo de Oliveira Johann, 2016, ISPD.

A Mesh-Buffer Displacement Optimization Strategy

Guilherme Flach, Marcelo de Oliveira Johann, Ricardo Reis, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization

Marcelo de Oliveira Johann, José Luís Almada Güntzel, Vinicius S. Livramento, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias

Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis, Renato Fernandes Hentschke, 2006, 2006 IFIP International Conference on Very Large Scale Integration.

Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities

Guilherme Flach, Tiago Reimann, Gracieli Posser, 2013, 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Blue Macaw: A Didactic Placement Tool Using Simulated Annealing

Marcelo de Oliveira Johann, Ricardo Reis, Renato Fernandes Hentschke, 2005, EDUTECH.

Cell placement on graphics processing units

Guilherme Flach, Marcelo de Oliveira Johann, Ricardo Reis, 2007, SBCCI '07.

Unbalacing the I/O Pins Partitioning for Minimizing Inter-Tier Vias in 3D VLSI Circuits

Marcelo de Oliveira Johann, Ricardo Reis, Renato Fernandes Hentschke, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

Admissibility Proofs for the LCS* Algorithm

Andrew B. Kahng, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis, 2000, IBERAMIA-SBIA.

Logical Core Algorithm: Improving Global Placement

Marcelo de Oliveira Johann, Ricardo Reis, Felipe Pinto, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

Maze routing steiner trees with effective critical sink optimization

Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis, Renato Fernandes Hentschke, 2007, ISPD '07.

An Incremental Timing-Driven flow using quadratic formulation for detailed placement

Paulo F. Butzen, Mateus Fogaça, Guilherme Flach, 2015, 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

A System for recording analog synthesizers with the Web

Marcelo de Oliveira Johann, Lucas Fialho Zawacki, 2012, ICMC.

LEGAL: An Algorithm for Simultaneous Net Routing

Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis, 2001 .

Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff

Marcelo de Oliveira Johann, Ricardo Reis, Renato Fernandes Hentschke, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Quadratic timing objectives for incremental timing-driven placement optimization

Mateus Fogaça, Guilherme Flach, Marcelo de Oliveira Johann, 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Posicionamento de Circuitos 3D Considerando o Planejamento de 3D-Vias

Marcelo de Oliveira Johann, Ricardo Reis, Renato Fernandes Hentschke, 2012, RITA.

Jezz: An effective legalization algorithm for minimum displacement

Guilherme Flach, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis, 2015, 2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI).

3D-Via Driven Partitioning for 3D VLSI Integrated Circuits

Marcelo de Oliveira Johann, Ricardo Reis, Gustavo Wilke, 2010, CLEI Electron. J..

A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation

Marcelo de Oliveira Johann, José Luís Almada Güntzel, Vinicius S. Livramento, 2014, ACM Trans. Design Autom. Electr. Syst..

Energy-efficient Level Shifter topology

Marcelo de Oliveira Johann, Ricardo Reis, Marco Terres, 2015, 2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

The Fidelity Property of the Elmore Delay Model in actual comparison of routing algorithms

Tiago Reimann, Marcelo de Oliveira Johann, Ricardo Reis, 2010, 2010 IEEE International Conference on Computer Design.

Analogue Audio Recording Using Remote Servers

Marcelo de Oliveira Johann, Lucas Fialho Zawacki, M. Johann, 2014, Ubiquitous Music.

Rsyn: An Extensible Physical Synthesis Framework

Mateus Fogaça, Guilherme Flach, Marcelo de Oliveira Johann, 2017, ISPD.

Fast and efficient Lagrangian Relaxation-based Discrete Gate Sizing

Marcelo de Oliveira Johann, José Luís Almada Güntzel, Vinicius S. Livramento, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Design of very deep pipelined multipliers for FPGAs

Sergio Bampi, Flávio Rech Wagner, Marcelo de Oliveira Johann, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.