Shihui Yin

发表

Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning

Yandong Luo, Xiaoyu Sun, Shimeng Yu, 2019, IEEE Micro.

Efficient continual learning at the edge with progressive segmented training

Jae-sun Seo, Shihui Yin, S. K. Venkataramanaiah, 2022, Neuromorphic Computing and Engineering.

Minimizing area and energy of deep learning hardware design using collective low precision and structured compression

Chaitali Chakrabarti, Visar Berisha, Jae-sun Seo, 2017, 2017 51st Asilomar Conference on Signals, Systems, and Computers.

PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference

Minkyu Kim, Jae-sun Seo, Mingoo Seok, 2021, 2021 Symposium on VLSI Circuits.

Improving the accuracy and robustness of RRAM-based in-memory computing against RRAM hardware noise and adversarial attacks

Shimeng Yu, Jae-sun Seo, Deliang Fan, 2021, Semiconductor Science and Technology.

An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays

Jae-sun Seo, Shihui Yin, Bipin Rajendran, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks

Jae-sun Seo, Mingoo Seok, Shihui Yin, 2020, IEEE Journal of Solid-State Circuits.

Vesti: An In-Memory Computing Processor for Deep Neural Networks Acceleration

Tushar Gupta, Minkyu Kim, Jae-sun Seo, 2019, 2019 53rd Asilomar Conference on Signals, Systems, and Computers.

Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays

Shihui Yin, Jae-Sun Seo, Bipin Rajendran, 2019, 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks

Xiaochen Peng, Shimeng Yu, Rui Liu, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

C3SRAM: In-Memory-Computing SRAM Macro Based on Capacitive-Coupling Computing

Mingoo Seok, Shihui Yin, Jae-Sun Seo, 2019, IEEE Solid-State Circuits Letters.

XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks

Jae-sun Seo, Mingoo Seok, Shihui Yin, 2018, 2018 IEEE Symposium on VLSI Technology.

An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition

Visar Berisha, Jae-sun Seo, Shihui Yin, 2020, IEEE Journal of Solid-State Circuits.

C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism

Jae-sun Seo, Mingoo Seok, Shihui Yin, 2020, IEEE Journal of Solid-State Circuits.

Automatic Compiler Based FPGA Accelerator for CNN Training

Eriko Nurvitadhi, Jae-sun Seo, Yu Cao, 2019, 2019 29th International Conference on Field Programmable Logic and Applications (FPL).

High-Throughput In-Memory Computing for Binary Deep Neural Networks With Monolithically Integrated RRAM and 90-nm CMOS

Shimeng Yu, Jae-sun Seo, Shihui Yin, 2019, IEEE Transactions on Electron Devices.

Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations

Chaitali Chakrabarti, Gregory K. Chen, Ram Krishnamurthy, 2017, 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS).

FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory

Eriko Nurvitadhi, Shihui Yin, Shreyas K. Venkataramanaiah, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design

Mingoo Seok, Shihui Yin, Jae-Sun Seo, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A 1.06 μW smart ECG processor in 65 nm CMOS for real-time biometrie authentication and personal cardiac monitoring

Yu Cao, Minkyu Kim, Jae-sun Seo, 2019, 2017 Symposium on VLSI Circuits.

A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation

Jae-sun Seo, Shihui Yin, Deepak Kadetotad, 2020, IEEE Journal of Solid-State Circuits.

Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks

Tushar Gupta, Jae-sun Seo, Mingoo Seok, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

XNOR-SRAM: In-Bitcell Computing SRAM Macro based on Resistive Computing Mechanism

Jae-sun Seo, Mingoo Seok, Shihui Yin, 2019, ACM Great Lakes Symposium on VLSI.

A 2.6 TOPS/W 16-Bit Fixed-Point Convolutional Neural Network Learning Processor in 65-nm CMOS

Shihui Yin, Jae-Sun Seo, Jae-sun Seo, 2020, IEEE Solid-State Circuits Letters.

Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks

Jae-sun Seo, Mingoo Seok, Deliang Fan, 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).

A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV and SRAM PUF for Authentication and Secret Key Generation

Sang Joon Kim, Shihui Yin, Jae-Sun Seo, 2019, 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC).

ECG Authentication Hardware Design With Low-Power Signal Processing and Neural Network Optimization With Low Precision and Structured Compression

Sang Joon Kim, Jae-sun Seo, Shihui Yin, 2020, IEEE Transactions on Biomedical Circuits and Systems.

Inference engine benchmarking across technological platforms from CMOS to RRAM

Xiaochen Peng, Xiaoyu Sun, Shimeng Yu, 2019, MEMSYS.

The Sooner The Better: Investigating Structure of Early Winning Lottery Tickets

Mauricio J. Serrano, Jinwook Oh, Shihui Yin, 2019 .

K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM

Jae-sun Seo, Mingoo Seok, Shihui Yin, 2019, 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

High-Throughput In-Memory Computing for Binary Deep Neural Networks With Monolithically Integrated RRAM and 90-nm CMOS

Shimeng Yu, Jae-sun Seo, Shihui Yin, 2019, IEEE Transactions on Electron Devices.

A 1.06- $\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring

Yu Cao, Minkyu Kim, Yang Liu, 2017, IEEE Journal of Solid-State Circuits.

PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference

Jae-sun Seo, Mingoo Seok, Shihui Yin, 2023, IEEE Journal of Solid-State Circuits.