M. Cao

A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 μm2 SRAM cell

M. D. Lei, W. Chang, Y. Chiu, 2007, 2007 IEEE International Electron Devices Meeting.

High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme

J. H. Chen, C. L. Chen, S. B. Wang, 2010, 2010 International Electron Devices Meeting.

A low operating power FinFET transistor module featuring scaled gate stack and strain engineering for 32/28nm SoC technology

Min Cao, Feng Yuan, Tsung-Lin Lee, 2010, 2010 International Electron Devices Meeting.

A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications

Min Cao, Sreedhar Natarajan, Hank Cheng, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Ultralow‐k Amorphous Boron Nitride Based on Hexagonal Ring Stacking Framework for 300 mm Silicon Technology Platform

T. Lee, Chuanghan Hsu, M. Cao, 2022, Advanced Materials Technologies.

5nm CMOS Production Technology Platform featuring full-fledged EUV, and High Mobility Channel FinFETs with densest 0.021µm2 SRAM cells for Mobile SoC and High Performance Computing Applications

Jun He, R. Chen, Geoffrey Yeap, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Fully Self-Aligned Via Integration for Interconnect Scaling Beyond 3nm Node

M. Cao, W. Shue, Y.H. Wu, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

Advanced patterning approaches for Cu/Low-k interconnects

C. Tsai, S. Shue, M. Cao, 2017, 2017 IEEE International Interconnect Technology Conference (IITC).

A Novel Methodology to Predict Process-Induced Warpage in Advanced BEOL Interconnects

M. H. Lin, R. Chen, M. Cao, 2023, IEEE International Reliability Physics Symposium.

A 3nm CMOS FinFlex™ Platform Technology with Enhanced Power Efficiency and Performance for Mobile SoC and High Performance Computing Applications

Shien-Yang Wu, M. Chiang, V. Chang, 2022, 2022 International Electron Devices Meeting (IEDM).