M. Orshansky

发表

A general probabilistic framework for worst case timing analysis

K. Keutzer, M. Orshansky, 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization

David G. Chinnery, Kurt Keutzer, Michael Orshansky, 2003, ISLPED '03.

Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation

M. Orshansky, Bin Zhang, 2008, ISQED 2008.

Robust Estimation of Parametric Yield under Limited Descriptions of Uncertainty

Wei-Shen Wang, M. Orshansky, M. Orshansky, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

Circuit performance variability decomposition

Costas J. Spanos, Michael Orshansky, Chenming Hu, 1999, 1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391).

Enabling efficient analog synthesis by coupling sparse regression and polynomial optimization

Constantine Caramanis, Ye Wang, Michael Orshansky, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

An Extension Of BSIM3 Model Incorporating Velocity Overshoot

Jeffrey Bokor, Michael Orshansky, Chenming Hu, 1997, Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications.

An accurate sparse matrix based framework for statistical static timing analysis

Sani R. Nassif, David Z. Pan, Anand Ramalingam, 2006, ICCAD.

Power Minimization with Multiple Supply Voltages and Multiple Threshold Voltages

K. Keutzer, D. Chinnery, M. Orshansky, 2003 .

An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis

S. Nassif, Gi-Joon Nam, A. Singh, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

ENHANCING PHYSICAL DEVICE IDENTITY TECHNOLOGY THROUGH PHYSICAL UNCLONABLE FUNCTIONS

M. Orshansky, 2016 .

FPGA Synthesis and CAD for Reconfigurable Systems

Luca Benini, Stephen A. Edwards, Yunheung Paek, 2009 .

Session details: Special session: DFM and variability: theory and practice

Michael Orshansky, Tanay Karnik, Chandu Visweswariah, 2005, DAC 2005.

A Strong Subthreshold Current Array PUF Resilient to Machine Learning Attacks

Michael Orshansky, Nan Sun, Xiaodan Xi, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

Estimating path delay distribution considering coupling noise

Sani R. Nassif, Jacob A. Abraham, Rajeshwary Tayade, 2007, GLSVLSI '07.

The Search for Alternative Computational Paradigms

Radu Marculescu, Gustavo de Veciana, Douglas L. Jones, 2008, IEEE Design & Test of Computers.

Approximate computing: An emerging paradigm for energy-efficient design

Jie Han, Michael Orshansky, Jie Han, 2013, 2013 18th IEEE European Test Symposium (ETS).

Architecting a reliable CMP switch architecture

Scott A. Mahlke, Todd M. Austin, Bin Zhang, 2007, TACO.

BulletProof: a defect-tolerant CMP switch architecture

Scott A. Mahlke, Todd M. Austin, Bin Zhang, 2006, The Twelfth International Symposium on High-Performance Computer Architecture, 2006..

Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits

Kurt Keutzer, Linda S. Milor, Michael Orshansky, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring

Jaeyoung Park, Mattan Erez, Michael Orshansky, 2013, International Symposium on Low Power Electronics and Design (ISLPED).

Design for Manufacturability and Statistical Design - A Constructive Approach

Sani R. Nassif, Duane S. Boning, Michael Orshansky, 2007, Series on integrated circuits and systems.

Statistical algorithms for circuit synthesis under process variation and high defect density

Ashish Kumar Singh, Michael Orshansky, A. Singh, 2007 .

Statistical technology mapping for parametric yield

David Blaauw, Kaviraj Chopra, A. Singh, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

A sequence dependent challenge-response PUF using 28nm SRAM 6T bit cell

David Blaauw, Dennis Sylvester, Michael Orshansky, 2017, 2017 Symposium on VLSI Circuits.

Strong subthreshold current array PUF with 265 challenge-response pairs resilient to machine learning attacks in 130nm CMOS

Nan Sun, Michael Orshansky, Xiaodan Xi, 2017, 2017 Symposium on VLSI Circuits.

Novel strong PUF based on nonlinearity of MOSFET subthreshold operation

Michael Orshansky, Mukund Kalyanaraman, M. Orshansky, 2013, 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

Leakage power reduction by dual-Vth designs under probabilistic analysis of Vth variation

Michael Orshansky, Wei-Shen Wang, Michael Liu, 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

Variability-Aware Training and Self-Tuning of Highly Quantized DNNs for Analog PIM pdf

Michael Orshansky, Zihao Deng, M. Orshansky, 2021, 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Power-based Malware Detection in Linux Boot

A. Gerstlauer, M. Orshansky, Mohit Tiwari, 2022 .

A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits

Michael Orshansky, Anirudh Devgan, Murari Mani, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An efficient algorithm for statistical minimization of total power under timing yield constraints

Michael Orshansky, Anirudh Devgan, Murari Mani, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Fast statistical timing analysis handling arbitrary delay correlations

Michael Orshansky, Arnab Bandyopadhyay, M. Orshansky, 2004, Proceedings. 41st Design Automation Conference, 2004..

Horizontal side-channel vulnerabilities of post-quantum key exchange protocols

Andreas Gerstlauer, Michael Orshansky, Aydin Aysu, 2018, 2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

Lattice PUF: A Strong Physical Unclonable Function Provably Secure against Machine Learning Attacks

Ye Wang, Michael Orshansky, Xiaodan Xi, 2019, 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

Training with Multi-Layer Embeddings for Model Reduction pdf

Mattan Erez, Ashish Kumar Singh, Michael Orshansky, 2020, ArXiv.

Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty

Vladik Kreinovich, Michael Orshansky, Wei-Shen Wang, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Interval-based robust statistical techniques for non-negative convex functions, with application to timing analysis of computer chips

Martine Ceberio, Gang Xiang, Michael Orshansky, 2006, SAC.

Models and algorithms for statistical timing and power analysis of digital integrated circuits

Michael Orshansky, Wei-Shen Wang, M. Orshansky, 2007 .

Binary Ring-LWE hardware with power side-channel countermeasures

Michael Orshansky, Aydin Aysu, Mohit Tiwari, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Provably Secure Strong PUF Based on LWE: Construction and Implementation

M. Orshansky, Ye Wang, Xiaodan Xi, 2023, IEEE Transactions on Computers.

Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange and Encapsulation Protocols

Andreas Gerstlauer, Michael Orshansky, Aydin Aysu, 2021, ACM Trans. Embed. Comput. Syst..

Securing AES against Localized EM Attacks through Spatial Randomization of Dataflow

Ge Li, Michael Orshansky, Vishnuvardhan V. Iyer, 2019, 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

Approximate logic synthesis under general error magnitude and frequency constraints

Andreas Gerstlauer, Michael Orshansky, Jin Miao, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Report for the NSF Workshop on Cross ‐ layer Power Optimization and Management

Jon C. Hiller, C. J. Holland, Benjamin C. Lee, 2012 .

Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks

Sanu Mathew, Jaydeep P. Kulkarni, Michael Orshansky, 2021, 2021 IEEE Custom Integrated Circuits Conference (CICC).

Efficient simulation of EM side-channel attack resilience

Amit Kumar, Michael Orshansky, Ali Yilmaz, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Modeling and synthesis of quality-energy optimal approximate adders

Ku He, Andreas Gerstlauer, Michael Orshansky, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation

Yu Cao, Dennis Sylvester, Takashi Sato, 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

Power-based Attacks on Spatial DNN Accelerators pdf

Michael Orshansky, Mohit Tiwari, Ge Li, 2021, ACM J. Emerg. Technol. Comput. Syst..

Multi-level approximate logic synthesis under general error constraints

Andreas Gerstlauer, Michael Orshansky, Jin Miao, 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Probabilistic strain optimization under constraint uncertainty

Soha Hassoun, Kyongbum Lee, Michael Orshansky, 2013, BMC Systems Biology.

Enhancing Cross-Category Learning in Recommendation Systems with Multi-Layer Embedding Training

M. Erez, A. Singh, M. Orshansky, 2023, ArXiv.

Analytical Modeling of SRAM Dynamic Stability

S. Nassif, A. Arapostathis, M. Orshansky, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

Joint Design-Time and Post-Silicon Minimization of Parametric Yield Loss using Adjustable Robust Optimization

M. Orshansky, A.K. Singh, M. Mani, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits

Kurt Keutzer, Linda S. Milor, Michael Orshansky, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Interval-based robust statistical techniques for non-negative convex functions, with application to timing analysis of computer chips

M. Orshansky, M. Ceberio, G. Xiang, 2006, SAC.

Static Timing Analysis Based on Partial Probabilistic Description of Delay Uncertainty

Vladik Kreinovich, Michael Orshansky, Wei-Shen Wang, 2006 .

Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters

Michael Orshansky, Wei-Shen Wang, M. Orshansky, 2007, J. Low Power Electron..

BulletProof: a defect-tolerant CMP switch architecture

Jason A. Blome, S. Mahlke, T. Austin, 2006, The Twelfth International Symposium on High-Performance Computer Architecture, 2006..

Assessing SEU Vulnerability via Circuit-Level Timing Analysis

Valeria Bertacco, Bin Zhang, Michael Orshansky, 2005 .

Gene modification identification under flux capacity uncertainty

Soha Hassoun, Kyongbum Lee, Michael Orshansky, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).