J. Ahn

Suboptimal filter design with pseudomeasurements for target tracking

T. Song, J. Ahn, C. Park, 1988 .

Systematic optimization of 1 Gbit perpendicular magnetic tunnel junction arrays for 28 nm embedded STT-MRAM and beyond

Seung H. Kang, M. Bangar, J. Ahn, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Systematic validation of 2x nm diameter perpendicular MTJ arrays and MgO barrier for sub-10 nm embedded STT-MRAM with practically unlimited endurance

M. Bangar, J. Ahn, C. Park, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

TMRC 2016│Schedule at a glance

Kang, Xue, C. S. Bhatia, 2016 .

Low RA Magnetic Tunnel Junction Arrays in Conjunction with Low Switching Current and High Breakdown Voltage for STT-MRAM at 10 nm and Beyond

C. Park, C. Ching, J. Ahn, 2018, 2018 IEEE Symposium on VLSI Technology.

Temperature Dependence of Critical Device Parameters in 1 Gb Perpendicular Magnetic Tunnel Junction Arrays for STT-MRAM

H. Chen, C. Park, A. Kontos, 2017, IEEE Transactions on Magnetics.