Z. Navabi

发表

Using data compression in automatic test equipment for system-on-chip testing

Fabrizio Lombardi, Waleed Meleis, Zainalabedin Navabi, 2004, IEEE Transactions on Instrumentation and Measurement.

Real-time embedded emotional controller

Caro Lucas, Zainalabedin Navabi, Arash Arami, 2010, Neural Computing and Applications.

Toward Embedded Emotionally Intelligent System

C. Lucas, M. Jamali, Z. Navabi, 2007 .

Line Oriented Structural Equivalence Fault Collapsing

M. R. Movahedin, Z. Navabi, M. Nadjarbashi, 2000 .

1 Line Oriented Structural Equivalence Fault Collapsing

M. R. Movahedin, Z. Navabi, M. Nadjarbashi, 2000 .

An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations

Mahmood Fathy, Armin Alaghi, Zainalabedin Navabi, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Using the inter- and intra-switch regularity in NoC switch testing

Z. Navabi, M. Hosseinabady, Atefe Dalirsani, 2007 .

BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs to Avoid Congestion

Masoud Daneshtalab, Caro Lucas, Pejman Lotfi-Kamran, 2008 .

Assignment coverage, a complementary coverage metric in formal verification

S. Mohammadi, Z. Navabi, H. Shojaei, 2007, 2007 International Conference on Design & Technology of Integrated Systems in Nanoscale Era.

Binary Taylor Diagrams ( BTD ) : An Efficient Way of Implementing Taylor Expansion Diagrams

Z. Navabi, B. Alizadeh, A. Hooshmand, 2022 .

Sign Bit Reduction Encoding for Low Power Ap p I i cat i o ns

A. Afzali-Kusha, Z. Navabi, M. Saneei, 2005 .

Concurrent Error Detection for LSTM Accelerators

Seyedeh Maryam Ghasemi, Mahboobe Sadeghipour Roodsari, Z. Navabi, 2022, 2022 IEEE European Test Symposium (ETS).

TED+: a data structure for microprocessor verification

Zainalabedin Navabi, Mohammad Hosseinabady, Mehran Massoumi, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

The Scalable and Reconfigurable DFT for Embedded A/MS Cores

Michel Renovell, Sattar Mirzakuchaki, Zainalabedin Navabi, 2006 .

Transaction Level Formal Verification using Timed Automata

Hamid Noori, Amirali Ghofrani, Zainalabedin Navabi, 2010 .

A New High Level Model Based on Integer Equations to Check CTL Properties in VHDL Environment

Z. Navabi, B. Alizadeh, M. R. Kakoee, 2003 .

Improving Taylor Expansion Diagrams for Boolean Function Manipulation

Z. Navabi, H. Shojaei, P. Lotfikamran, 2004 .

Hardware description in verilog: an overview

Zainalabedin Navabi, Z. Navabi, 2000 .

Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment

Fabrizio Lombardi, Zainalabedin Navabi, Pedram A. Riahi, 2003, Embedded Systems and Applications.

An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements

Jaan Raik, Zainalabedin Navabi, Maksim Jenihhin, 2019, 2019 IEEE East-West Design & Test Symposium (EWDTS).

Memory Testing by Means of Memory BIST

Zainalabedin Navabi, Z. Navabi, 2011 .

VHDL: Analysis and Modeling of Digital Systems

Zainalabedin Navabi, Z. Navabi, 1992 .

Using integer equations to check PSL properties in RT level design

Zainalabedin Navabi, Bijan Alizadeh, Z. Navabi, 2004, 4th IEEE International Workshop on System-on-Chip for Real-Time Applications.

Path selection and sensor insertion flow for age monitoring in FPGAs

Elaheh Bozorgzadeh, Zainalabedin Navabi, Mohammad Ebrahimi, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Word-level symbolic simulation in processor verification

Zainalabedin Navabi, Bijan Alizadeh, Z. Navabi, 2004 .

Property checking based on hierarchical integer

Zainalabedin Navabi, Bijan Alizadeh, Z. Navabi, 2004, Proceedings. Fourth International Conference on Application of Concurrency to System Design, 2004. ACSD 2004..

CTL Property Checking Based on a New High Level Model Without Equation Solving

Z. Navabi, B. Alizadeh, 2003 .

Data compression for system-on-chip testing using ATE

Fabrizio Lombardi, Waleed Meleis, Zainalabedin Navabi, 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

Reliability in Application Specific Mesh-Based NoC Architectures

Paolo Prinetto, Zainalabedin Navabi, Fatemeh Refan, 2008, 2008 14th IEEE International On-Line Testing Symposium.

Self-Adjusting Monitor for Measuring Aging Rate and Advancement

Mehdi Kamal, Zainalabedin Navabi, Somayeh Sadeghi-Kohan, 2017, IEEE Transactions on Emerging Topics in Computing.

An off-line MDSI interconnect BIST incorporated in BS 1149.1

Nasser Masoumi, Zainalabedin Navabi, Somayeh Sadeghi Kohan, 2014, 2014 19th IEEE European Test Symposium (ETS).

BS 1149.1 extensions for an online interconnect fault detection and recovery

Majid Namaki-Shoushtari, Somayeh Sadeghi Kohan, Zainalabedin Navabi, 2012, 2012 IEEE International Test Conference.

Improving polynomial datapath debugging with HEDs

Masahiro Fujita, Zainalabedin Navabi, Payman Behnam, 2014, 2014 19th IEEE European Test Symposium (ETS).

Emotion on FPGA: Model driven approach

Arash Arami, Caro Lucas, Masood Deh-Yadegari, 2009, Expert Syst. Appl..

A Novel Modeling Approach for System-Level Application Mapping Targeted for Configurable Architecture

Zainalabedin Navabi, Hossein Sabaghian-Bidgoli, Seyed Ali Shahabi, 2014, Canadian Journal of Electrical and Computer Engineering.

TLM 2.0 simple sockets synthesis to RTL

Paolo Prinetto, Amirali Ghofrani, Zainalabedin Navabi, 2009, 2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era.

An advanced method for synthesizing TLM2-based interfaces

Zainalabedin Navabi, Nadereh Hatami, Z. Navabi, 2008, Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08).

Reliable NoC architecture utilizing a robust rerouting algorithm

Mahmood Fathy, Armin Alaghi, Zainalabedin Navabi, 2008, Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08).

Assertion-based verification for system-level designs

Zainalabedin Navabi, Hasan Sohofi, Z. Navabi, 2014, Fifteenth International Symposium on Quality Electronic Design.

Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment

M. H. Haghbayan, Zainalabedin Navabi, Fatemeh Javaheri, 2010, 2010 19th IEEE Asian Test Symposium.

Generating test patterns for sequential circuits using random patterns by PLI functions

M. H. Haghbayan, Zainalabedin Navabi, Ramyar Saeedi, 2010, 2010 East-West Design & Test Symposium (EWDTS).

"Plug & Test" at System Level via Testable TLM Primitives

Paolo Prinetto, Stefano Di Carlo, Zainalabedin Navabi, 2008, 2008 IEEE International Test Conference.

Low overhead DFT using CDFG by modifying controller

Fabrizio Lombardi, Zainalabedin Navabi, Mohammad Hosseinabady, 2007, IET Comput. Digit. Tech..

A Flow Graph Technique for DFT Controller Modification

Fabrizio Lombardi, Mohammad Hosseinabady, Pejman Lotfi-Kamran, 2005, Proceedings 2005 IEEE International SOC Conference.

Selecting Representative Critical Paths for Sensor Placement Provides Early FPGA Aging Information

Zainalabedin Navabi, Morteza Ebrahimi, Z. Navabi, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Online Profiling for cluster-specific variable rate refreshing in high-density DRAM systems

Zainalabedin Navabi, Rasool Sharifi, Z. Navabi, 2017, 2017 22nd IEEE European Test Symposium (ETS).

TruncApp: A truncation-based approximate divider for energy efficient DSP applications

Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies

Behzad Ebrahimi, Ali Afzali-Kusha, Massoud Pedram, 2015, Integr..

LUT Input Reordering to Reduce Aging Impact on FPGA LUTs

Mohammad Ebrahimi, Zainalabedin Navabi, Rezgar Sadeghi, 2020, IEEE Transactions on Computers.

SENSIBle: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs

Mohammad Ebrahimi, Zainalabedin Navabi, Nader Bagherzadeh, 2017, IEEE Transactions on Computers.

BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs

Masoud Daneshtalab, Zainalabedin Navabi, Caro Lucas, 2008, 2008 Design, Automation and Test in Europe.

Dynamic routing algorithm for avoiding hot spots in on-chip networks

A. Afzali-Kusha, Mohammad Hossein Neishaburi, M. Daneshtalab, 2006, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006..

Logic Built-in Self-test

Zainalabedin Navabi, Z. Navabi, 2011 .

BILBO-friendly hybrid BIST architecture with asymmetric polynomial reseeding

Mahmood Fathy, Zainalabedin Navabi, Mohammadreza Najafi, 2012, The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012).

Fault simulation for VHDL based test bench and BIST evaluation

Zainalabedin Navabi, Mina Zolfy, Shahrzad Mirkhani, 2001, Proceedings 10th Asian Test Symposium.

Stall Power Reduction in Pipelined Architecture Processors

Ali Afzali-Kusha, Amir-Mohammad Rahmani, Zainalabedin Navabi, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Test instruction set (TIS) for high level self-testing of CPU cores

Zainalabedin Navabi, Hadi Esmaeilzadeh, Saeed Shamshiri, 2004, 13th Asian Test Symposium.

Dynamic Power Reduction of Stalls in Pipelined Architecture Processors

Ali Afzali-Kusha, Amir-Mohammad Rahmani, Zainalabedin Navabi, 2011 .

Processor Description in APDL for Design Space Exploration of Embedded Processors

Maghsoud Abbaspour, Zainalabedin Navabi, Hassan Sohofi, 2007 .

APDL: A Processor Description Language For Design Space Exploration of Embedded Processors

Maghsoud Abbaspour, Zainalabedin Navabi, Hasan Sohofi, 2007, FDL.

A Selective Trigger Scan Architecture for VLSI Testing

Fabrizio Lombardi, Zainalabedin Navabi, Mohammad Hosseinabady, 2008, IEEE Transactions on Computers.

Reducing test power, time and data volume in SoC testing using selective trigger scan architecture

Zainalabedin Navabi, Mohammad Hosseinabady, Shervin Sharifi, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

Embedded Data Fusion Toolbox: A Model Driven Architecture

Z. Navabi, M. R. Jamali, C. Lucas, 2009, 2009 Fourth International Conference on Embedded and Multimedia Computing.

Online Test Macro Scheduling and Assignment in MPSoC Design

M. H. Haghbayan, Zainalabedin Navabi, Seyyed Alireza Hoseini, 2011, 2011 Asian Test Symposium.

A Survey of Testability Measurements at Various Abstraction Levels

Z. Navabi, Naghmeh Karimi, Pedram Riyahi, 2003 .

Mapping Transaction Level Faults to Stuck-At Faults in Communication Hardware

Majid Namaki-Shoushtari, Zainalabedin Navabi, Parastoo Kamranfar, 2011, 2011 Asian Test Symposium.

Simultaneous reduction of dynamic and static power in scan structures

Ali Afzali-Kusha, Zainalabedin Navabi, Mohammad Hosseinabady, 2005, Design, Automation and Test in Europe.

An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing

Z. Navabi, Mahnaz Sadoughi Yarandi, A. Alaghi, 2006, 2006 15th Asian Test Symposium.

Embedded Core Design with FPGAs

Zainalabedin Navabi, Z. Navabi, 2006 .

Verilog HDL for Design and Test

Zainalabedin Navabi, Z. Navabi, 2011 .

Basics of Test and Role of HDLs

Zainalabedin Navabi, Z. Navabi, 2011 .

Configurable Systolic Matrix Multiplication

Zainalabedin Navabi, Parastoo Kamranfar, Ali Shahabi, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

Soft Error Analysis on Communication Channels in On-Chip Communication Networks

Zainalabedin Navabi, Saeed Safari, Mohammadreza Najafi, 2012, 2012 15th Euromicro Conference on Digital System Design.

Soft-error-immune communication network using unbalanced protection selection

Z. Navabi, M. Najafi, S. Ghandali, 2012, The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012).

A UML Based System Level Failure Rate Assessment Technique for SoC Designs

Zainalabedin Navabi, Mohammad Hosseinabady, Mohammad Hossein Neishaburi, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

An Ef ﬁ cient RTL Design for a Wearable Brain – Computer Interface

Z. Navabi, Tahereh Vasei, Mohammad Ali Saber, 2022 .

Pico-Programmable Neurons to Reduce Computations for Deep Neural Network Accelerators

Z. Navabi, Alireza Nahvy, 2024, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.