Antonio Lloris-Ruíz

Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies

Fred J. Taylor, Antonio García, Javier Ramírez, 2003, J. VLSI Signal Process..

Solution of Switching Based on a Tabular

Antonio Lloris-Ruíz, P. Trabado, 1993 .

IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores

Antonio García, Luis Parrilla, Encarnación Castillo, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers

Antonio García, Encarnación Castillo, Antonio Lloris-Ruíz, 2005, PATMOS.

Intellectual Property Protection for RNS Circuits on FPGAs

Antonio García, Encarnación Castillo, Antonio Lloris-Ruíz, 2004, FPL.

Design and Implementation of RNS-Based Adaptive Filters

Antonio García, Javier Ramírez, Uwe Meyer-Bäse, 2003, FPL.

Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic

Fred J. Taylor, Antonio García, Javier Ramírez, 2002, J. VLSI Signal Process..

A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems

Antonio García, Graham A. Jullien, Luis Parrilla, 2002, PATMOS.

An efficient RNS architecture for the computation of discrete wavelet transforms on programmable devices

Javier Ramírez, Antonio García, Antonio Lloris-Ruíz, 2000, 2000 10th European Signal Processing Conference.

Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform

Antonio García, Luis Parrilla, Javier Ramírez, 2000, FPL.

A new architecture to compute the discrete cosine transform using the quadratic residue number system

Luis Parrilla, Antonio Lloris-Ruíz, Javier Ramírez, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic

Fred J. Taylor, Antonio García, Uwe Meyer-Bäse, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

Test-Pattern Generation Based on Reed-Muller Coefficients

Julio Ortega Lopera, Francisco J. Pelayo, Antonio Lloris-Ruíz, 1993, IEEE Trans. Computers.