P. Hanumolu

发表

A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration

Amr Elshazly, Pavan Kumar Hanumolu, Wenjing Yin, 2011, IEEE Journal of Solid-State Circuits.

13-1 A Self-referenced VCO-based Temperature Sensor with 0 . 034 oC / mV Supply Sensitivity in 65 nm CMOS

P. Hanumolu, K. Makinwa, T. Anand, 2015 .

A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy

Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon, 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers

Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu, 2018, IEEE Journal of Solid-State Circuits.

AN ABSTRACT OF THE THESIS OF Gowtham Vemulapalli for the degree of Master of Science in Electrical and Computer Engineering presented on October 17, 2003. Title: Accurately Tunable Low-voltage Continuous-time Filters

Manu, Yuhua, Vivek, 2009 .

A Sub-Picosecond Resolution 0.5-1.5GHz Digital-to-Phase Converter

Un-Ku Moon, Gu-Yeon Wei, P.K. Hanumolu, 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS

Amr Elshazly, Pavan Kumar Hanumolu, Thomas Toifl, 2011, 2011 IEEE International Solid-State Circuits Conference.

A multiplexer-based digital passive linear counter (PLINCO)

Pavan Kumar Hanumolu, Un-Ku Moon, Skyler Weaver, 2012 .

A second-order temperature compensated 1μW/MHz 100MHz RC oscillator with ±140ppm inaccuracy from -40°C to 95°C

Kyu-Sang Park, P. Hanumolu, Amr Khashaba, 2021, 2021 IEEE Custom Integrated Circuits Conference (CICC).

A 10 MS / s 11b 0 . 19 mm 2 Algorithmic ADC with Improved Clocking

Pavan Kumar Hanumolu, Un-Ku Moon, Min Gyu Kim, 2006 .

A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance

Amr Elshazly, Pavan Kumar Hanumolu, Wenjing Yin, 2011, IEEE Journal of Solid-State Circuits.

A Stochastic Time-to-Digital Converter for Digital Phase-Locked Loops

G. Ahn, K. Mayaram, P. Hanumolu, 2005 .

Title : A Stochastic Time-to-Digital Converter for Digital Phase-Locked Loops

G. Ahn, U. Moon, K. Mayaram, 2005 .

Op-amp Free Sc Biquad Lpf and Delta-sigma Adc

P. Hanumolu, Gowtham Vemulapalli, D. Chang, 2004 .

VLSI Design 2009 Technical Program Committee

Susmita Sur-Kolay, Rajendran Panda, Puneet Gupta, 2009 .

Continuous-Time Input Pipeline ADCs

Pavan Kumar Hanumolu, Un-Ku Moon, David Gubbins, 2010, IEEE Journal of Solid-State Circuits.

A continuous-time input pipeline ADC with inherent anti-alias filtering

Pavan Kumar Hanumolu, Un-Ku Moon, Sunwoo Kwon, 2009, 2009 IEEE Custom Integrated Circuits Conference.

A continuous-time input pipeline ADC

Pavan Kumar Hanumolu, Un-Ku Moon, David Gubbins, 2008, 2008 IEEE Custom Integrated Circuits Conference.

Guaranteeing Local Differential Privacy on Ultra-Low-Power Systems

Woo-Seok Choi, Pavan Kumar Hanumolu, Rakesh Kumar, 2018, 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA).

A Fast Startup CMOS Crystal Oscillator Using Two-Step Injection

Ahmed Elkholy, Pavan Kumar Hanumolu, Karim M. Megawer, 2019, IEEE Journal of Solid-State Circuits.

8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS

Ahmed Elkholy, Pavan Kumar Hanumolu, Daniel Coombs, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A Wide-Tracking Range Clock and Data Recovery Circuit

Un-Ku Moon, Gu-Yeon Wei, P.K. Hanumolu, 2008, IEEE Journal of Solid-State Circuits.

A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators—Analysis, Design, and Measurement Techniques

Amr Elshazly, Pavan Kumar Hanumolu, Brian Young, 2014, IEEE Journal of Solid-State Circuits.

Title : Oscillators and Phase Locked Loops for Space Radiation Environments

G. Ahn, P. Hanumolu, Tom Brown, 2005 .

34-GBd Linear Transimpedance Amplifier for 200-Gb/s DP-16-QAM Optical Coherent Receivers

Pavan Kumar Hanumolu, Yong Wang, Alexander Rylyakov, 2019, IEEE Journal of Solid-State Circuits.

Design techniques for clocking high performance signaling systems

Pavan Kumar Hanumolu, P. Hanumolu, 2006 .

Analysis of PLL clock jitter in high-speed serial links

Pavan Kumar Hanumolu, Gu-Yeon Wei, Un-Ku Moon, 2003, IEEE Trans. Circuits Syst. II Express Briefs.

A Modulo-Based Architecture for Analog-to-Digital Conversion

Pavan Kumar Hanumolu, Andrew C. Singer, Gregory W. Wornell, 2018, IEEE Journal of Selected Topics in Signal Processing.

A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications

Pavan Kumar Hanumolu, Karthikeyan Reddy, Sachin Rao, 2015, IEEE Journal of Solid-State Circuits.

A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators

Tejasvi Anand, Amr Elshazly, Pavan Kumar Hanumolu, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS

Ahmed Elkholy, Pavan Kumar Hanumolu, Mostafa Gamal Ahmed, 2020, IEEE Journal of Solid-State Circuits.

23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS

Ahmed Elkholy, Woo-Seok Choi, Pavan Kumar Hanumolu, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links

Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, 2015, IEEE Journal of Solid-State Circuits.

Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers

Pavan Kumar Hanumolu, Kartikeya Mayaram, Ting Wu, 2009, IEEE Journal of Solid-State Circuits.

A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop

Pavan Kumar Hanumolu, Kartikeya Mayaram, Ting Wu, 2007, 2007 IEEE Custom Integrated Circuits Conference.

The effect of power supply noise on ring oscillator phase noise

Un-Ku Moon, P.K. Hanumolu, M. Brownlee, 2004, The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004..

A 32-MHz, 34-μW Temperature-Compensated RC Oscillator Using Pulse Density Modulated Resistors

P. Hanumolu, Amr Khashaba, Nilanjan Pal, 2022, IEEE Journal of Solid-State Circuits.

3.5 A 34µW 32MHz RC Oscillator with ±530ppm Inaccuracy from −40°C to 85°C and 80ppm/V Supply Sensitivity Enabled by Pulse-Density Modulated Resistors

Pavan Kumar Hanumolu, Junheng Zhu, Amr Khashaba, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 6 $\mu$ W ±50 ppm/°C ±1500 ppm/V 1.5 MHz $RC$ Oscillator Using Self-Regulation

Ahmed Elkholy, Pavan Kumar Hanumolu, Ahmed Elmallah, 2019, IEEE Trans. Circuits Syst. II Express Briefs.

Hybrid Dickson Switched-Capacitor Converter With Wide Conversion Ratio in 65-nm CMOS

Pavan Kumar Hanumolu, Pourya Assem, Robert C. N. Pilawa-Podgurski, 2020, IEEE Journal of Solid-State Circuits.

A 1-μW/MHz RC Oscillator With Three-Point Trimmed 2.1-ppm/°C and Single-Point Trimmed 8.7-ppm/°C Stability From40 °C to 95 °C

Kyu-Sang Park, P. Hanumolu, Amr Khashaba, 2023, IEEE Journal of Solid-State Circuits.

A 20-μs Turn-On Time, 24-kHz Resolution, 1.5–100-MHz Digitally Programmable Temperature-Compensated Clock Generator

Kyu-Sang Park, P. Hanumolu, Ahmed Abdelrahman, 2023, IEEE Journal of Solid-State Circuits.

10.3 A 94.2%-peak-efficiency 1.53A direct-battery-hook-up hybrid Dickson switched-capacitor DC-DC converter with wide continuous conversion ratio in 65nm CMOS

Pavan Kumar Hanumolu, Robert C. N. Pilawa-Podgurski, Yutian Lei, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 10-MHz 2–800-mA 0.5–1.5-V 90% Peak Efficiency Time-Based Buck Converter With Seamless Transition Between PWM/PFM Modes

Woo-Seok Choi, Pavan Kumar Hanumolu, Seong Joong Kim, 2018, IEEE Journal of Solid-State Circuits.

A 1.2A buck-boost LED driver with 13% efficiency improvement using error-averaged SenseFET-based current sensing

Pavan Kumar Hanumolu, Sachin Rao, Qadeer Ahmad Khan, 2011, 2011 IEEE International Solid-State Circuits Conference.

A 91.15% Efficient 2.3–5-V Input 10–35-V Output Hybrid Boost Converter for LED-Driver Applications

P. Hanumolu, R. Pilawa-Podgurski, W. McIntyre, 2021, IEEE Journal of Solid-State Circuits.

High-Performance CMOS TIA for Data Center Optical Interconnects

P. Hanumolu, V. Boccuzzi, K. Lakshmikumar, 2022, 2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS).

A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling

Ahmed Elkholy, Pavan Kumar Hanumolu, Romesh Kumar Nandwana, 2021, IEEE Journal of Solid-State Circuits.

A Deterministic Digital Background Calibration Technique for VCO-Based ADCs

Pavan Kumar Hanumolu, Brian Young, Karthikeyan Reddy, 2014, IEEE Journal of Solid-State Circuits.

A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation

Amr Elshazly, Pavan Kumar Hanumolu, Wenjing Yin, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm2 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS

Pavan Kumar Hanumolu, Robert C. N. Pilawa-Podgurski, Qadeer Ahmad Khan, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

Automated Design and Optimization of Low-Noise Oscillators

Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Sub-Picosecond Resolution 0.5–1.5 GHz Digital-to-Phase Converter

Un-Ku Moon, Gu-Yeon Wei, P.K. Hanumolu, 2008, IEEE Journal of Solid-State Circuits.

A 2.5–5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler

Ahmed Elkholy, Pavan Kumar Hanumolu, Daniel Coombs, 2019, IEEE Journal of Solid-State Circuits.

10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS

Ahmed Elkholy, Tejasvi Anand, Pavan Kumar Hanumolu, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 6.75–8.25-GHz −250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier

Ahmed Elkholy, Pavan Kumar Hanumolu, Ahmed Elmallah, 2018, IEEE Journal of Solid-State Circuits.

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC

Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, 2015, IEEE Journal of Solid-State Circuits.

A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider

Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu, 2016, IEEE Journal of Solid-State Circuits.

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method

Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, 2015, IEEE Journal of Solid-State Circuits.

Analog Filter Design Using Ring Oscillator Integrators

Pavan Kumar Hanumolu, Mrunmay Talegaonkar, Brian Drost, 2012, IEEE Journal of Solid-State Circuits.

Signal Processing Foundations for Time-Based Signal Representations: Neurobiological parallels to engineered systems designed for energy efficiency or hardware simplicity

Andrew C. Singer, Lav R. Varshney, Pavan K. Hanumolu, 2019, IEEE Signal Processing Magazine.

A 0.016 mm2 0.26- $\mu$ W/MHz 60–240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS

Pavan Kumar Hanumolu, Junheng Zhu, Woo-Seok Choi, 2019, IEEE Journal of Solid-State Circuits.

A 7 pA/$\surd\text{Hz}$ Asymmetric Differential TIA for 100Gb/s PAM-4 links with −14dBm Optical Sensitivity in 16nm CMOS

P. Hanumolu, K. Lakshmikumar, R. Nandwana, 2023, 2023 IEEE International Solid- State Circuits Conference (ISSCC).

Low dropout regulators

Pavan Kumar Hanumolu, P. Hanumolu, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS

Ahmed Elkholy, Pavan Kumar Hanumolu, Daniel Coombs, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

A 3.2-GHz 405 fsrms Jitter –237.2 dB FoMJIT Ring-Based Fractional-N Synthesizer

Karim M. Megawer, P. Hanumolu, Ahmed Elkholy, 2022, IEEE Journal of Solid-State Circuits.

A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking

Amr Elshazly, Pavan Kumar Hanumolu, Wenjing Yin, 2011, IEEE Journal of Solid-State Circuits.

A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC

Amr Elshazly, Pavan Kumar Hanumolu, Kartikeya Mayaram, 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Digital PLL With a Stochastic Time-to-Digital Converter

Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon, 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers

Ahmed Elkholy, Tejasvi Anand, Pavan Kumar Hanumolu, 2015, IEEE Journal of Solid-State Circuits.

3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS

Luca Benini, Woo-Seok Choi, Pavan Kumar Hanumolu, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity

Kofi A. A. Makinwa, Tejasvi Anand, Pavan Kumar Hanumolu, 2016, IEEE Journal of Solid-State Circuits.

Sensitivity Analysis for Oscillators

Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops

Amr Elshazly, Pavan Kumar Hanumolu, Brian Young, 2013, IEEE Journal of Solid-State Circuits.

A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning

Un-Ku Moon, P.K. Hanumolu, M. Brownlee, 2006, IEEE Journal of Solid-State Circuits.

A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning

Un-Ku Moon, P.K. Hanumolu, M. Brownlee, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

A 10 MS/s 11-bit 0.19 mm $^{2}$ Algorithmic ADC With Improved Clocking Scheme

Un-Ku Moon, Min Gyu Kim, P.K. Hanumolu, 2009, IEEE Journal of Solid-State Circuits.

A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth

Amr Elshazly, Pavan Kumar Hanumolu, Brian Young, 2010, IEEE Custom Integrated Circuits Conference 2010.