Sanghune Park

A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX

Chulwoo Kim, Jeongsik Yoo, Hyunsu Park, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology

Jinho Choi, Kwanyeob Chae, Sanghyun Lee, 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller

Jinho Choi, Jihun Oh, Sangsoo Park, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique

Jaehong Park, Kihwan Seong, Sanghune Park, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).