D. LaTulipe

Advanced gate stacks with fully silicided (FUSI) gates and high-/spl kappa/ dielectrics: enhanced performance at reduced gate leakage

H. Nayfeh, M. Ieong, J. Kedzierski, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

T. Graves-abe, C. Kothandaraman, B. Himmel, 2014 .

GaAs multiple quantum well waveguide modulators on silicon substrates

W. I. Wang, D. LaTulipe, S. Basu, 1990 .

Demonstration of an optical chip-to-chip link in a 3D integrated electronic-photonic platform

Douglas Coolbaugh, Vladimir Stojanovic, Sen Lin, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

Ion implantation and annealing of undoped (Al,Ga)As/GaAs heterostructures

D. Frank, T. Jackson, P. Solomon, 1987 .

ELECTRON VELOCITY AT HIGH ELECTRIC FIELDS IN AlGaAs/GaAs MODULATION-DOPED HETEROSTRUCTURES

Wei Wang, S. L. Wright, W. T. Masselink, 1988 .

Comparison of liquid- and vapor-phase silylation processes for 193-nm positive-tone lithography

Mark A. Hartney, Roderick R. Kunz, Douglas C. LaTulipe, 1993, Advanced Lithography.

Overlay as the key to drive wafer scale 3D integration

Steven E. Steen, Anna W. Topol, David J. Frank, 2007 .

Threshold shifting in pseudomorphic semiconductor-insulator-semiconductor heterostructure field-effect transistors

T. Jackson, P. Solomon, S. Wright, 1991 .

Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology

Toshiaki Kirihata, John Golz, Alex Hubbard, 2013, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).