Z. Cao

Process Integration Considerations for 300 mm TSV Manufacturing

S. Pamarthy, S. Ramaswami, J. Dukovic, 2009, IEEE Transactions on Device and Materials Reliability.

Thermal stability of copper Through-Silicon Via barriers during IC processing

Eric Beyne, Deniz S. Tezcan, Philippe Soussan, 2011, 2011 IEEE International Interconnect Technology Conference.

Formation of TSV for the stacking of advanced logic devices utilizing bumpless wafer-on-wafer technology

Takayuki Ohba, S. W. Kim, Hideki Kitada, 2012 .

Through-silicon-via technology for 3D integration

G. Mori, M. Naik, Z. Cao, 2010, 2010 IEEE International Memory Workshop.

On the thermal stability of physically-vapor-deposited diffusion barriers in 3D Through-Silicon Vias during IC processing

E. Beyne, A. Redolfi, K. Croes, 2013 .