B. Doris

发表

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

Syed Muhammad Zain Zafar, M. Hargrove, C. Ouyang, 2007, 2007 IEEE Symposium on VLSI Technology.

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

L. H. Vanamurth, D. Yang, T. Adam, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond

M. Ieong, E. Cartier, V. Narayanan, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

T. Adam, T. Standaert, M. Khare, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

High performance FDSOI CMOS technology with metal gate and high-k

Anna W. Topol, P. Kirsch, K. Guarini, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

A. Toffoli, J. Cluzel, O. Faynot, 2010, 2010 Symposium on VLSI Technology.

Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

H. Sunamura, T. Yamamoto, B. Haran, 2010, 2010 Symposium on VLSI Technology.

Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain

T. Adam, J. Holt, B. Haran, 2006, 2009 Symposium on VLSI Technology.

Assessment of fully-depleted planar CMOS for low power complex circuit operation

K. Tabakman, S. Wu, T. Kanarsky, 2011, 2011 International Electron Devices Meeting.

Extreme scaling with ultra-thin Si channel MOSFETs

H.-S.P. Wong, Ying Zhang, Leathen Shi, 2002, Digest. International Electron Devices Meeting,.

A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates

C. Cabral, V. Narayanan, S. Zafar, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Examination of hole mobility in ultra-thin body SOI MOSFETs

M. Ieong, W. Haensch, T. Kanarsky, 2002, Digest. International Electron Devices Meeting,.

Randomly oriented Angstrom‐scale microroughness at the Si(100)/SiO2 interface probed by optical second harmonic generation

J. Dadap, B. Doris, J. Lowell, 1994 .

A survey of non‐destructive surface characterization methods used to insure reliable gate oxide fabrication for silicon IC devices

B. Doris, A. Diebold, 1993 .

Application of optical second harmonic generation in characterization of Si(100)/SiO/sub 2/ interfacial microroughness

J. Dadap, B. Doris, J. Lowell, 1993, Proceedings of LEOS '93.

Key parameters affecting STT-MRAM switching efficiency and improved device performance of 400°C-compatible p-MTJs

D. Edelstein, C. Kothandaraman, P. Hashemi, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Silicon Device Scaling to the Sub-10-nm Regime

M. Ieong, J. Kedzierski, Min Yang, 2004, Science.

HOT-carrier degradation in undoped-body ETSOI FETS and SOI FINFETS

H. Jagannathan, J. Stathis, K. Cheng, 2010, 2010 IEEE International Reliability Physics Symposium.

Aggressively Scaled Strained-Silicon-on-Insulator Undoped-Body High- $\kappa$/Metal-Gate nFinFETs for High-Performance Logic Applications

Chun-Chen Yeh, Huiming Bu, T. Standaert, 2011, IEEE Electron Device Letters.

Device design considerations for ultra-thin SOI MOSFETs

V. Narayanan, M. Steen, R. Jammy, 2003, IEEE International Electron Devices Meeting 2003.

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

K. Maitra, P. Kulkarni, T. Yamashita, 2010, 2010 Symposium on VLSI Technology.

Evaluation of sSOI wafers for 22nm node and beyond

W. Schwarzenbach, B. Nguyen, M. Vinet, 2012, 2012 IEEE International SOI Conference (SOI).

High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond

M. Khare, S. Luning, O. Faynot, 2013, 2013 IEEE International Electron Devices Meeting.

Gate length scaling accelerated to 30 nm regime using ultra-thin film PD-SOI technology

Woo-Hyeong Lee, S.K.H. Fung, P. Agnello, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Improved atomic force microscopy imaging using carbon‐coated probe tips

Bruce B. Doris, Rama I. Hegde, B. Doris, 1995 .

(Invited) Silicon Germanium FinFET Device Physics, Process Integration and Modeling Considerations

Pierre Morin, Ali Khakifirooz, Bruce B. Doris, 2014 .

Examination of flatband and threshold voltage tuning of HfO2∕TiN field effect transistors by dielectric cap layers

V. Narayanan, B. Linder, M. Copel, 2007 .

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

T. Nagumo, N. Loubet, W. Schwarzenbach, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Effects of in situ doping from B2H6 and PH3 on hydrogen desorption and the low-temperature growth mode of Si on Si(100) by remote plasma enhanced chemical vapor deposition

S. Banerjee, B. Doris, J. L. Erskine, 1997 .

Nucleation and Growth of CVD Si Thin Films: AFM, SE and Tem Analysis

W. McGahan, B. Doris, W. Paulson, 1994 .

Silicon Device Scaling to the Sub‐10‐nm Regime

M. Ieong, J. Kedzierski, Min Yang, 2005 .

Implant approaches and challenges for 20nm node and beyond ETSOI devices

M. Khare, S. Luning, B. Haran, 2011, IEEE 2011 International SOI Conference.

Mapping of electrostatic potential in deep submicron CMOS devices by electron holography.

Jing Li, C S Murthy, David J Smith, 2002, Physical review letters.

Ti and NiPt/Ti liner silicide contacts for advanced technologies

F. Chafik, S. Jain, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

Ultra-low resistivity in-situ phosphorus doped Si and SiC epitaxy for source/drain formation in advanced 20nm n-type field effect transistor devices

Nicolas Loubet, Bruce B. Doris, Walter Kleemeier, 2012 .

Subnanometer-resolution depth profiling of boron atoms and lattice defects in silicon ultrashallow junctions by ion beam techniques

L. Vanamurthy, B. Doris, P. Ronsheim, 2013 .

Thermal Stability of Copper Contact Metallization Using Ru-Containing Liner

C. Hu, B. Haran, D. Canaperi, 2011 .

Optical metrology of Ni and NiSi thin films used in the self-aligned silicidation process

Alain C. Diebold, Vimal Kamineni, B. Doris, 2010 .

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

D. Liu, P. Oldiges, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

O. Faynot, Y. Escarabajal, B. Lherron, 2014, 2014 IEEE International Electron Devices Meeting.

A review of the mechanical stressors efficiency applied to the ultra-thin body & buried oxide fully depleted silicon on insulator technology

Pierre Morin, Sylvain Maitrejean, Frederic Allibert, 2016 .

UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below

O. Rozeau, O. Faynot, M. Vinet, 2012, 2012 International Electron Devices Meeting.

High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET

M. Vinet, L. Grenouillet, T. Nagumo, 2012, 2012 International Electron Devices Meeting.

Full metal gate with borderless contact for 14 nm and beyond

B. Haran, V. Narayanan, J. Bruley, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

B. Jagannathan, N. Loubet, P. Kulkarni, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond

Junjun Li, Davood Shahrjerdi, Robert Gauthier, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Molybdenum contamination in low‐temperature epitaxial silicon films grown by remote plasma chemical vapor deposition

S. Banerjee, B. Doris, R. Sharma, 1996 .

Spin-transfer torque MRAM with reliable 2 ns writing for last level cache applications

R. P. Robertazzi, N. Marchack, H. K. Lee, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

K. Maitra, T. Yamashita, V. S. Basker, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

A mobility enhancement strategy for sub-14nm power-efficient FDSOI technologies

O. Rozeau, O. Faynot, G. Ghibaudo, 2014, 2014 IEEE International Electron Devices Meeting.

Impact of back bias on ultra-thin body and BOX (UTBB) devices

M. Vinet, T. Skotnicki, L. Grenouillet, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

14nm FDSOI technology for high speed and energy efficient applications

J. Mazurier, O. Faynot, A. Pofelski, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Use of metal-oxide-semiconductor capacitors in the analysis of low-temperature epitaxial Si films deposited by remote plasma-enhanced chemical vapor deposition

S. Banerjee, B. Doris, R. Sharma, 1997 .

Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance

N. Loubet, T. Yamashita, J. A. Ott, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).