H. Bu

发表

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

Syed Muhammad Zain Zafar, M. Hargrove, C. Ouyang, 2007, 2007 IEEE Symposium on VLSI Technology.

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

L. H. Vanamurth, D. Yang, T. Adam, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

S. Narasimha, M. Hargrove, R. Pal, 2011, 2011 International Electron Devices Meeting.

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

T. Adam, T. Standaert, M. Khare, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

H. Sunamura, T. Yamamoto, B. Haran, 2010, 2010 Symposium on VLSI Technology.

Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain

T. Adam, J. Holt, B. Haran, 2006, 2009 Symposium on VLSI Technology.

Assessment of fully-depleted planar CMOS for low power complex circuit operation

K. Tabakman, S. Wu, T. Kanarsky, 2011, 2011 International Electron Devices Meeting.

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

D. Corliss, T. Standaert, R. Wong, 2017, 2017 Symposium on VLSI Technology.

HOT-carrier degradation in undoped-body ETSOI FETS and SOI FINFETS

H. Jagannathan, J. Stathis, K. Cheng, 2010, 2010 IEEE International Reliability Physics Symposium.

Aggressively Scaled Strained-Silicon-on-Insulator Undoped-Body High- $\kappa$/Metal-Gate nFinFETs for High-Performance Logic Applications

Chun-Chen Yeh, Huiming Bu, T. Standaert, 2011, IEEE Electron Device Letters.

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

K. Maitra, P. Kulkarni, T. Yamashita, 2010, 2010 Symposium on VLSI Technology.

Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs

T. B. Hook, T. Yamashita, T. E. Standaert, 2013, 2013 IEEE International Electron Devices Meeting.

Channel doping impact on FinFETs for 22nm and beyond

P. Oldiges, T. B. Hook, T. Yamashita, 2012, 2012 Symposium on VLSI Technology (VLSIT).

High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond

M. Khare, S. Luning, O. Faynot, 2013, 2013 IEEE International Electron Devices Meeting.

The Interaction Challenges with Novel Materials in Developing High‐Performance and Low‐Leakage High‐k/Metal Gate CMOS Transistors

M. Khare, E. Cartier, V. Narayanan, 2012 .

Understanding and mitigating High-k induced device width and length dependencies for FinFET replacement metal gate technology

V. Narayanan, T. Ando, A. Madan, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices

A. Young, H. Jagannathan, J. Demarest, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

Gate-Last I/O Transistors based on Stacked Gate-All-Around Nanosheet Architecture for Advanced Logic Technologies

A. Chou, B. Haran, N. Loubet, 2021, International Electron Devices Meeting.

Stacked Gate-All-Around Nanosheet pFET with Highly Compressive Strained Si1-xGex Channel

B. Haran, N. Loubet, K. Zhao, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Ti and NiPt/Ti liner silicide contacts for advanced technologies

F. Chafik, S. Jain, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

D. Liu, P. Oldiges, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

B. Lherron, D. Chanemougame, P. Oldiges, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Sub- $10^{-9}~\Omega $ -cm2 n-Type Contact Resistivity for FinFET Technology

B. Haran, J. Demarest, O. Gluschenkov, 2016, IEEE Electron Device Letters.

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

P. Oldiges, C. Park, N. Loubet, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond

Phil Oldiges, Wilfried Haensch, Andres Bryant, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

B. Jagannathan, N. Loubet, P. Kulkarni, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond

Junjun Li, Davood Shahrjerdi, Robert Gauthier, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices

M. Belyansky, B. Haran, N. Loubet, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

The future transistors

K. Banerjee, T. Ghani, M. Vinet, 2023, Nature.

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

K. Maitra, T. Yamashita, V. S. Basker, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

SiGe FinFET for practical logic libraries by mitigating local layout effect

Andreas Knorr, Jie Yang, John R. Sporre, 2017, 2017 Symposium on VLSI Technology.

A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs

S. Narasimha, J. Johnson, M. Khare, 2015, Symposium on VLSI Technology.

Challenges and Opportunities for Stacked Transistor: DTCO and Device

A. Young, B. Haran, T. Hook, 2021, Symposium on VLSI Technology.

Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology

H. Jagannathan, J. Demarest, M. Sankarapandian, 2022, International Electron Devices Meeting.

Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications

C. Park, N. Loubet, B. Haran, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Impact of back bias on ultra-thin body and BOX (UTBB) devices

M. Vinet, T. Skotnicki, L. Grenouillet, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications

M. Khare, B. Haran, N. Loubet, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Critical Elements for Next Generation High Performance Computing Nanosheet Technology

V. Narayanan, D. Guo, E. Leobandung, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm

M. Belyansky, C. Prindle, A. Young, 2019, 2019 Symposium on VLSI Technology.

Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors

B. Haran, N. Loubet, D. Guo, 2021, ECS Transactions.

Air spacer for 10nm FinFET CMOS and beyond

M. Wang, T. Yamashita, H. Bu, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT

Jie Yang, Terence B. Hook, Andreas Knorr, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Sub-25nm FinFET with advanced fin formation and short channel effect engineering

K. Maitra, P. Kulkarni, T. Yamashita, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.