N. Daval

发表

Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO2 gate stack

O. Faynot, J. Hartmann, C. Fenouillet-Béranger, 2007, 2007 IEEE International Electron Devices Meeting.

Molecular Beam Epitaxy Growth of High Mobility Compound Semiconductor Devices for Integration with Si CMOS

Amy W. K. Liu, J. Fastenau, D. Lubyshev, 2009 .

10a.1 Advanced Semiconductor on Insulator Substrates for Low Power and High Performance Digital CMOS Applications

W. Schwarzenbach, K. Bourdelle, B. Nguyen, 2011 .

Germanium Multiple-Gate Field-Effect Transistors Formed on Germanium-on-Insulator Substrate

Y. Yeo, B. Nguyen, B. Liu, 2013, IEEE Transactions on Electron Devices.

SiC Power Devices on QUASIC and SiCOI Smart-Cut® Substrates: First Demonstrations

J. Bluet, E. Bano, N. Daval, 2003 .

Comparative Simulation Analysis of Process-Induced Variability in Nanoscale SOI and Bulk Trigate FinFETs

Asen Asenov, Andrew R. Brown, Bich-Yen Nguyen, 2013, IEEE Transactions on Electron Devices.

Silicon-on-insulator (SOI) fin-on-oxide field effect transistors (FinFETs)

Andrew R. Brown, A. Asenov, B. Cheng, 2014 .

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

T. Nagumo, N. Loubet, W. Schwarzenbach, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Ultra-Thin SOI/BOX Layers and Next Generations Planar Fully Depleted Substrates

Bich-Yen Nguyen, Christophe Maleville, Walter Schwarzenbach, 2012 .

New layer transfers obtained by the SmartCut process

F. Fournel, B. Ghyselen, C. Morales, 2003 .

Engineering strained silicon on insulator wafers with the Smart CutTM technology

Y. Bogumilowicz, N. Kernevez, Pascal Besson, 2004 .

Comparison between <100> and <110> oriented channels in highly strained FDSOI pMOSFETs

A. Toffoli, O. Faynot, G. Ghibaudo, 2012, 2012 IEEE International SOI Conference (SOI).

Splitting kinetics of Si0.8Ge0.2 layers implanted with H or sequentially with He and H

N. Cherkashin, K. Bourdelle, C. Mazure, 2008 .

Method of reduction of the roughness of a thick layer of insulation

S. Kerdilès, N. Daval, C. Aulnette, 2005 .

Strain engineering of ultra-thin silicon-on-insulator structures using through-buried-oxide ion implantation and crystallization

Y. Yeo, B. Nguyen, N. Daval, 2013 .

Monolithic III-V/Si integration

J. Fastenau, D. Lubyshev, B. Brar, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

SiGe wet oxidation at low temperature : application to SiGeOI thinning

N. Daval, I. Cayrefourcq, E. Guiot, 2004 .

Thermal considerations for advanced SOI substrates designed for III-V/Si heterointegration

E. Augendre, M. Urteaga, B. Brar, 2009, 2009 IEEE International SOI Conference.

Monolithic integration of InP-based transistors on Si substrates using MBE

T. E. Kazior, Bobby Brar, Dmitri Lubyshev, 2009 .

Stress Metrology : The challenge for the next generation of engineered wafers

Vincent Paillard, Ian Cayrefourcq, Nicolas Daval, 2004 .

Germanium Multiple-Gate Field-Effect Transistor With In Situ Boron-Doped Raised Source/Drain

Y. Yeo, B. Nguyen, B. Liu, 2013, IEEE Transactions on Electron Devices.

Advanced FD-SOI and Beyond Low Temperature SmartCut™ Enables High Density 3-D SoC Applications

W. Schwarzenbach, B. Nguyen, C. Maleville, 2019, IEEE Journal of the Electron Devices Society.

Atomic Scale Thickness Control of SOI Wafers for Fully Depleted Applications

Bich-Yen Nguyen, Christophe Maleville, Walter Schwarzenbach, 2013 .

Ultra-Thin Film SOI/BOX Substrate Development, Its Application and Readiness

Bich-Yen Nguyen, Christophe Maleville, Walter Schwarzenbach, 2011 .

High-Performance Germanium $\Omega$ -Gate MuGFET With Schottky-Barrier Nickel Germanide Source/Drain and Low-Temperature Disilane-Passivated Gate Stack

Bin Liu, Xiao Gong, Yee-Chia Yeo, 2012, IEEE Electron Device Letters.

Asymetrically strained high performance Germanium gate-all-around nanowire p-FETs featuring 3.5 nm wire width and contractible phase change liner stressor (Ge2Sb2Te5)

Y. Yeo, K. Bourdelle, B. Nguyen, 2013, 2013 IEEE International Electron Devices Meeting.

High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding

O. Rozeau, O. Faynot, F. Andrieu, 2008, 2008 IEEE International Electron Devices Meeting.

Monolithically Integrated III-V and Si CMOS Devices on Silicon on Lattice Engineered Substrates (SOLES)

J. Fastenau, W. K. Liu, D. Lubyshev, 2009 .