H. Meer

发表

Stress dependence and poly-pitch scaling characteristics of (110) PMOS drive current

S. Narasimha, A. Waite, J. Johnson, 2007, 2007 IEEE Symposium on VLSI Technology.

A 2-D analytical threshold voltage model for fully-depleted SOI MOSFETs with Halos or pockets

K. De Meyer, H. van Meer, K. Meyer, 2001 .

Threshold voltage model for deep-submicron fully depleted SOI CMOS transistors including the effect of source/drain fringing fields into the buried oxide

K. Meyer, H. Meer, 2001 .

Ultra-thin film fully-depleted SOI CMOS with raised G/S/D device architecture for sub-100 nm applications

K. De Meyer, H. van Meer, K. Meyer, 2001 .

Investigation Of Charge Control-Related Performances In Double-Gate SOI MOSFETs

Denis Flandre, Jean-Pierre Raskin, Valeriya Kilchytska, 2003 .

Shrinking from 0.25 µm down to 0.12 µm SOI CMOS technology node: a contribution to 1/f noise in partially depleted n-MOSFETs

Christina De Meyer, C. Raynaud, Jalal Jomaah, 2002 .

The spacer/replacer concept: a viable route for sub-100 nm ultrathin-film fully-depleted SOI CMOS

K. Meyer, H. Meer, 2002 .

Two-Dimensional Model for the Subthreshold Slope in Deep-Submicron Fully-Depleted SO 1 MOSFET ' s

K. Meyer, Kasteelpark Arenberg, H. Meer, 2007 .

Two-Dimensional Model for the Subthreshold Slope in Deep-Submicron Fully-Depleted SOI MOSFET’s

K. Meyer, H. Meer, 2001 .

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

D. Mocuta, C. Norris, C. Radens, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Novel High-Performance Analog Devices for Advanced Low-Power High-k Metal Gate Complementary Metal–Oxide–Semiconductor Technology

F. S. Johnson, R. Wachnik, K. Barla, 2011 .

The 1/f/sup 1.7/ noise in submicron SOI MOSFETs with 2.5 nm nitrided gate oxide

E. Simoen, C. Claeys, K. De Meyer, 2002 .

The Noise in Submicron SOI MOSFETs With 2.5 nm Nitrided Gate Oxide

Cor Claeys, Eddy Simoen, K. De Meyer, 2002 .

New layout dependency in high-k/Metal Gate MOSFETs

M. Sherony, F. Arnaud, F. Matsuoka, 2011, 2011 International Electron Devices Meeting.

Fin Bending Mitigation and Local Layout Effect Alleviation in Advanced FinFET Technology through Material Engineering and Metrology Optimization

H. Meer, B. Colombeau, Y. Tasi, 2019, 2019 Symposium on VLSI Technology.

FinFET IO Device Performance Gain with Heated Implantation

Y. Zhang, H. Gossmann, H. Meer, 2018, International Conference on Innovations in Information Technology.

The scaled FinFET well formation using heated implantation

Y. Zhang, H. Gossmann, H. Meer, 2022, MRS Advances.

Influence of device engineering on the analog and RF performances of SOI MOSFETs

Denis Flandre, Jean-Pierre Raskin, Stéphane Adriaensen, 2003 .

Low-frequency gate current noise of InP based HEMTs

E. Simoen, K. V. D. Zanden, M. Valenza, 1999 .

Low-frequency noise overshoot in ultrathin gate oxide silicon-on-insulator metal–oxide–semiconductor field-effect transistors

Eddy Simoen, C. Claeys, Abdelkarim Mercha, 2003 .

NFET effective work function improvement via stress memorization technique in replacement metal gate technology

Y. Liu, S. Jain, S. Samavedam, 2013, 2013 Symposium on VLSI Technology.