J. Mori

A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology

M. Nagamatsu, Y. Toyoshima, J. Mori, 1991 .

A 320 Mflops Cmos Floating-point Processing Unit For Superscalar Processors

J. Mori, Y. Kondo, N. Ide, 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.