P. Saha

发表

High speed ASIC design of complex multiplier using Vedic Mathematics

A. Dandapat, A. Banerjee, P. Saha, 2011, IEEE Technology Students' Symposium.

Revisiting Analytical Models of N-Type Symmetric Double-Gate MOSFETs Shaded Conditions

P. Saha, Rekib Uddin Ahmed, Rekib Ahmed, 2020 .

Single Event Transient Response of SiGe Voltage References and Its Impact on the Performance of Analog and Mixed-Signal Circuits

M. Turowski, A. Raman, G. Vizkelethy, 2009, IEEE Transactions on Nuclear Science.

An 8–16 GHz SiGe Low Noise Amplifier With Performance Tuning Capability for Mitigation of Radiation-Induced Performance Loss

J. Cressler, P. Saha, N. Lourenco, 2012, IEEE Transactions on Nuclear Science.

A K-Band nMOS SPDT Switch and Phase Shifter Implemented in 130nm SiGe BiCMOS Technology

J. Cressler, J. Comeau, W.-M.L. Kuo, 2009, 2009 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

Evaluating the Effects of Single Event Transients in FET-Based Single-Pole Double-Throw RF Switches

David M. Fleischhauer, S. Buchner, J. Cressler, 2014, IEEE Transactions on Nuclear Science.

Design and Implementation of RF Front End for Ultra Wide Band Systems

T. K. Bhattacharyya, A. Basu, P. Saha, 2005 .

Improved Floating Point Multiplier Design based on Canonical Sign Digit 22

A. Dandapat, P. Saha, P. Bhattacharyya, 2014 .

Vedic division methodology for high-speed very large scale integration applications

A. Dandapat, P. Saha, P. Bhattacharyya, 2014 .

Mixed-mode stress degradation mechanisms in pnp SiGe HBTs

J. Cressler, R. Wise, P. Saha, 2009, 2009 IEEE International Reliability Physics Symposium.

Improved matrix multiplier design for high-speed digital signal processing applications

Arindam Banerjee, Prabir Saha, Partha Bhattacharyya, 2014, IET Circuits Devices Syst..

A 6–20 GHz Adaptive SiGe Image Reject Mixer for a Self-Healing Receiver

John D. Cressler, R. M. Diestelhorst, Duane C. Howard, 2012, IEEE Journal of Solid-State Circuits.

A tunable, SiGe X-band image reject mixer

John D. Cressler, J. Cressler, P. Saha, 2010, 2010 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM).

Implementation of high speed processor for computing convolution sum for DSP applications

Abhijit Sharma, P. Saha, D. Kumar, 2015, IMCOM.

An adaptive, wideband SiGe image reject mixer for a self-healing receiver

John D. Cressler, Subramaniam Shankar, Ryan Diestelhorst, 2011, 2011 IEEE Bipolar/BiCMOS Circuits and Technology Meeting.

ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics

Arindam Banerjee, Prabir Saha, Partha Bhattacharyya, 2011, Microelectron. J..

Implementation Aspects of Multi-bit Adders Using UTBSOI Transistors

Rekib Uddin Ahmed, Prabir Saha, P. Saha, 2020 .

Low-loss, wideband SPDT switches and switched-line phase shifter in 180-nm RF CMOS on SOI technology

John D. Cressler, Prabir Saha, Adilson S. Cardoso, 2014, 2014 IEEE Radio and Wireless Symposium (RWS).

A Low Quantum Cost Implementation of Reversible Binary-Coded-Decimal Adder

Prabir Saha, Sheba Diamond Thabah, P. Saha, 2020, Period. Polytech. Electr. Eng. Comput. Sci..

New design approaches of reversible BCD encoder using Peres and Feynman gates

Prabir Saha, Sheba Diamond Thabah, P. Saha, 2020, ICT Express.

Investigations on Decimal Multipliers through Novel Partial Product Generators

P. Saha, P. Samanta, 2021, Journal of The Institution of Engineers (India): Series B.

Discrete Fourier transformation processor based on complex radix (−1 + j) number system

Prabir Saha, Anidaphi Shadap, P. Saha, 2017 .

X/Ku-Band Four-Channel Transmit/Receive SiGe Phased-Array IC

O. Gurbuz, P. Saha, Sriram Muralidharan, 2019, 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

HARDWARE IMPLEMENTATION OF METHODOLOGIES OF FIXED POINT DIVISION ALGORITHMS

Deepak Kumar, Anup Dandapat, Prabir Saha, 2017 .

Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications

Arindam Banerjee, Prabir Saha, Partha Bhattacharyya, 2011, 2011 International Symposium on Electronic System Design.

HIGH SPEED MULTIPLIER USING HIGH ACCURACY OATING POINT LOGARITHMIC NUMBER SYSTEM

Prabir Saha, Anup Dandapat, Arindam Banerjee, 2014 .