P. Bhattacharyya

High speed ASIC design of complex multiplier using Vedic Mathematics

A. Dandapat, A. Banerjee, P. Saha, 2011, IEEE Technology Students' Symposium.

Improved Floating Point Multiplier Design based on Canonical Sign Digit 22

A. Dandapat, P. Saha, P. Bhattacharyya, 2014 .

Vedic division methodology for high-speed very large scale integration applications

A. Dandapat, P. Saha, P. Bhattacharyya, 2014 .

Improved matrix multiplier design for high-speed digital signal processing applications

Arindam Banerjee, Prabir Saha, Partha Bhattacharyya, 2014, IET Circuits Devices Syst..

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

Vinay Kumar, Partha Bhattacharyya, Anup Dandapat, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics

Arindam Banerjee, Prabir Saha, Partha Bhattacharyya, 2011, Microelectron. J..

Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications

Arindam Banerjee, Prabir Saha, Partha Bhattacharyya, 2011, 2011 International Symposium on Electronic System Design.

HIGH SPEED MULTIPLIER USING HIGH ACCURACY OATING POINT LOGARITHMIC NUMBER SYSTEM

Prabir Saha, Anup Dandapat, Arindam Banerjee, 2014 .