R. Gauthier

发表

Technology scaling of advanced bulk CMOS on-chip ESD protection down to the 32nm node

Junjun Li, K. Chatty, R. Gauthier, 2009, 2009 31st EOS/ESD Symposium.

White Paper 1: A Case for Lowering Component Level HBM/MM ESD Specifications and Requirements Industry Council on ESD Target Levels

H. Gossner, R. Gauthier, R. Gaertner, 2013 .

High-current characterization of dual-damascene copper interconnects in SiO/sub 2/- and low-k interlevel dielectrics for advanced CMOS semiconductor technologies

M. Hargrove, S. Voldman, R. Gauthier, 1999, 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).

High-current transmission line pulse characterization of aluminum and copper interconnects for advanced CMOS semiconductor technologies

Steven H. Voldman, Robert J. Gauthier, S. Voldman, 1998, 1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173).

Reliability aspects of gate oxide under ESD pulse stress

H. Gossner, T. Pompl, K. Chatty, 2007 .

Investigation of voltage overshoots in diode triggered silicon controlled rectifiers (DTSCRs) under very fast transmission line pulsing (VFTLP)

Junjun Li, K. Chatty, R. Gauthier, 2009, 2009 31st EOS/ESD Symposium.

Investigation of SOI SCR triggering and current sustaining under DC and TLP conditions

Robert Gauthier, James Di Sarro, Junjun Li, 2013, 2013 35th Electrical Overstress/Electrostatic Discharge Symposium.

Effect of embedded-SiGe (eSiGe) on ESD TLP and VFTLP characteristics of diode-triggered silicon controlled rectifiers (DTSCRs)

R. Gauthier, Rahul Mishra, Junjun Li, 2012, Electrical Overstress / Electrostatic Discharge Symposium Proceedings 2012.

Evaluation of SCR-Based ESD Protection Devices in 90nm and 65nm CMOS Technologies

R. Gauthier, K. Chatty, E. Rosenbaum, 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

Capacitance investigation of diodes and SCRs for ESD protection of high frequency circuits in sub-100nm bulk CMOS technologies

R. Gauthier, K. Chatty, S. Mitra, 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

Degradation of High-$k$/Metal Gate nMOSFETs Under ESD-Like Stress in a 32-nm Technology

Junjun Li, K. Chatty, R. Gauthier, 2011, IEEE Transactions on Device and Materials Reliability.

Characterization of high-k/metal gate stack breakdown in the time scale of ESD events

Souvick Mitra, Yang Yang, Dimitris E. Ioannou, 2010, 2010 IEEE International Reliability Physics Symposium.

ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology

Souvick Mitra, Robert Gauthier, Elyse Rosenbaum, 2009, 2009 31st EOS/ESD Symposium.

Human Body Model ESD protection concepts in SOI and bulk CMOS at the 130 nm node

M. Muhammad, R. Gauthier, K. Chatty, 2003, 2003 IEEE International Conference on SOI.

SOI Poly-defined Diode for ESD Protection in High Speed I/Os

C. Putnam, E. Rosenbaum, R. Gauthier, 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

ESD device performance analysis in a 14nm FinFET SOI CMOS technology: Fin-based versus planar-based

You Li, Junjun Li, R. Gauthier, 2014, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2014.

Impact of stress engineering on high-k metal gate ESD diodes in 32nm SOI technology

C. Putnam, R. Gauthier, S. Mitra, 2009, 2009 31st EOS/ESD Symposium.

Reliability aspects of gate oxide under ESD pulse stress

Thomas Pompl, Wolfgang Stadler, Kai Esmark, 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

A 7nm CMOS technology platform for mobile and high performance compute application

J. Zeng, S. Samavedam, B. Senapati, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond

Junjun Li, Davood Shahrjerdi, Robert Gauthier, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Influence of Package Trace Properties on CDM Stress

Robert Gauthier, Bill Reynolds, James P. Di Sarro, 2014, IEEE Transactions on Device and Materials Reliability.

Optical and electrical testing of latchup in I/O interface circuits

Franco Stellari, Alan J. Weger, Peilin Song, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

ESD protection using grounded gate, gate non-silicided (GG-GNS) ESD NFETs in 45nm SOI technology

R. Gauthier, C. Seguin, S. Mitra, 2008, EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium.

Investigation of External Latchup Robustness of Dual and Triple Well Designs in 65nm Bulk CMOS Technology

K. Chatty, C. Seguin, R. Halbach, 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

Semiconductor process and structural optimization of shallow trench isolation-defined and polysilicon-bound source/drain diodes for ESD networks

R. Gauthier, J. Pekarik, J. Pekarik, 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

On The Interaction of ESD, NBTI and HCI in 65nm Technology

R. Gauthier, K. Chatty, C. Seguin, 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.