D. Pan

发表

Buffer block planning for interconnect-driven floorplanning

Jason Cong, David Z. Pan, Tianming Kong, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Synthetic Biology Design and Analysis: A Case Study of Frequency Entrained Biological Clock

Xi Chen, David Z. Pan, Peng Yu, 2008, 2008 IEEE International Conference on Bioinformatics and Biomedicine.

QuantumNAS: Noise-Adaptive Search for Robust Quantum Circuits pdf

David Z. Pan, Frederic T. Chong, Song Han, 2021, 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA).

Exploiting Wavelength Division Multiplexing for Optical Logic Synthesis

Derong Liu, Ray T. Chen, David Z. Pan, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

GAN-SRAF: Subresolution Assist Feature Generation Using Generative Adversarial Networks

Mohamed Baker Alawieh, D. Pan, Qi-Xing Huang, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

ML-based Routing Guidance Generation Data Pre-processing Trained ML Model Guided AMS Routing Guided Detailed Routing Post-processing ML Model Training AMS Circuit Layout Database Dashed : Training Solid : Inference Fr am ew or k Placement Routed Layout

D. Pan, Biying Xu, Nan Sun, 2019 .

Training Data Data Machine Learning Algorithm Learned Model Prediction Training Prediction

D. Pan, Yibo Lin, Xiaoqing Xu, 2017 .

Signal Identification Track Info Signal Group Info Backbone Generation Synergistic Routing Candidate Generation Complete ? Streak Output Y Primal-Dual Solution Update

Vinicius S. Livramento, D. Pan, Derong Liu, 2018 .

Wavelength-division-multiplexing based electronic photonic network for high speed computing

Ray T. Chen, D. Pan, Zheng Zhao, 2020 .

Comparison of microrings and microdisks for high-speed optical modulation in silicon photonics

Ray T. Chen, R. Soref, D. Pan, 2018 .

ELIAD: Efficient lithography aware detailed router with compact post-OPC printability prediction

Kun Yuan, David Z. Pan, Yongchan Ban, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Electrical impact of line-edge roughness on sub-45-nm node standard cells

David Z. Pan, Yongchan Ban, Savithri Sundareswaran, 2010 .

High Performance Lithography Hotspot Detection with Hierarchically Refined Machine Learning Methods

Fedor G. Pikus, David Z. Pan, Duo Ding, 2010 .

PARR: Pin access planning and regular routing for self-aligned double patterning

David Z. Pan, Xiaoqing Xu, Jhih-Rong Gao, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Decomposition for Triple Patterning Lithography

D. Pan, Bei Yu, D. Ding, 2013 .

Wavelength-division-multiplexing (WDM)-based integrated electronic–photonic switching network (EPSN) for high-speed data processing and transportation

Ray T. Chen, D. Pan, Zheng Zhao, 2020 .

Design for Manufacturability with E-Beam Lithography

D. Pan, Bei Yu, 2016 .

A 1-GS/s 20 MHz-BW Capacitive-Input Continuous-Time $\Delta\Sigma$ ADC Using a Novel Parasitic Pole-Mitigated Fully Differential VCO

D. Pan, Biying Xu, Nan Sun, 2019, IEEE Solid-State Circuits Letters.

Modeling of electromigration in through-silicon-via based 3D IC

Jiwoo Pak, Sung Kyu Lim, David Z. Pan, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

Highly flexible polymeric optical waveguide for out-of-plane optical interconnects.

Xiaolong Wang, Ray T. Chen, Duo Ding, 2010, Optics express.

Polymeric waveguides with embedded micro-mirrors formed by Metallic Hard Mold.

Xiaolong Wang, Ray T. Chen, Haiyu Huang, 2010, Optics express.

An accurate sparse matrix based framework for statistical static timing analysis

Sani R. Nassif, David Z. Pan, Anand Ramalingam, 2006, ICCAD.

True crosstalk aware incremental placement with noise map

David Z. Pan, Paul G. Villarrubia, Haoxing Ren, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

A novel intensity based optical proximity correction algorithm with speedup in lithography simulation

David Z. Pan, Peng Yu, YU Peng, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

Pyramids: An efficient computational geometry-based approach for timing-driven placement

C. Alpert, C. Sze, Zhuo Li, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Interconnect design for deep submicron ICs

Jason Cong, Cheng-Kok Koh, Lei He, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Comprehensive Standard Cell Characterization Considering Random Line-Edge Roughness Lithography Variation

D. Pan, S. Sundareswaran, Y. Ban, 2009 .

TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC

S. Lim, Moongon Jung, D. Pan, 2014, CACM.

Guest Editorial

David Z. Pan, Patrick H. Madden, P. Madden, 2008, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Layout Decomposition for Triple Patterning Lithography

D. Pan, Bei Yu, D. Ding, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL

D. Pan, Jiaqi Gu, Mingjie Liu, 2022, 2022 ACM/IEEE 4th Workshop on Machine Learning for CAD (MLCAD).

HRViT: Multi-Scale High-Resolution Vision Transformer

Meng Li, Liangzhen Lai, V. Chandra, 2021 .

A Compact Butterfly-Style Silicon Photonic–Electronic Neural Chip for Hardware-Efficient Deep Learning

Ray T. Chen, D. Pan, Jiaqi Gu, 2021, ACS Photonics.

Double patterning technology friendly detailed routing

Minsik Cho, D. Pan, Y. Ban, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper

H. Amrouch, J. Henkel, Bei Yu, 2022, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis

S. Nassif, Gi-Joon Nam, A. Singh, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

FPGA Synthesis and CAD for Reconfigurable Systems

Luca Benini, Stephen A. Edwards, Yunheung Paek, 2009 .

NeurOLight: A Physics-Agnostic Neural Operator Enabling Parametric Photonic Device Simulation

Ray T. Chen, D. Boning, D. Pan, 2022, NeurIPS.

Delving into Effective Gradient Matching for Dataset Condensation

D. Pan, Jiaqi Gu, Mingjie Liu, 2022, ArXiv.

A timing engine inspired graph neural network model for pre-routing slack prediction

D. Pan, Jiaqi Gu, Yibo Lin, 2022, DAC.

QuEst: Graph Transformer for Quantum Circuit Reliability Estimation

Xuehai Qian, Yiyu Shi, D. Pan, 2022, ArXiv.

Graph Transformer for Quantum Circuit Reliability Prediction

Xuehai Qian, Yiyu Shi, D. Pan, 2022 .

S 2 -PM: semi-supervised learning for efficient performance modeling of analog and mixed signal circuits.

David Z. Pan, Mohamed Baker Alawieh, Xiyuan Tang, 2019, ASP-DAC 2019.

Fuse and Mix: MACAM-Enabled Analog Activation for Energy-Efficient Neural Acceleration

Ray T. Chen, D. Pan, Jiaqi Gu, 2022, 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design

Anima Anandkumar, K. Sastry, Zong-Yi Li, 2022, ArXiv.

Sleep transistor sizing using timing criticality and temporal currents

David Z. Pan, Bin Zhang, Anand Ramalingam, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization pdf

Azadeh Davoodi, Zhiru Zhang, Sergio Bampi, 2020, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Machine learning for mask/wafer hotspot detection and mask synthesis

David Z. Pan, Xiaoqing Xu, Yibo Lin, 2017, Photomask Technology.

Semisupervised Hotspot Detection With Self-Paced Multitask Learning

Yayi Wei, David Z. Pan, Yibo Lin, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Semi-supervised hotspot detection with self-paced multi-task learning

Ying Chen, Yayi Wei, David Z. Pan, 2019, ASP-DAC.

Machine Learning for Yield Learning and Optimization

David Z. Pan, Mohamed Baker Alawieh, Wei Ye, 2018, 2018 IEEE International Test Conference (ITC).

Wire sizing with scattering effect for nanoscale interconnection

David Z. Pan, Sean X. Shi, D. Pan, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Towards Memory-Efficient Neural Networks via Multi-Level in situ Generation pdf

David Z. Pan, Chenghao Feng, Zixuan Jiang, 2021, 2021 IEEE/CVF International Conference on Computer Vision (ICCV).

Robust analytical gate delay modeling for low voltage circuits

David Z. Pan, Anand Ramalingam, Anirudh Devgan, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Wire width planning for interconnect performance optimization

Jason Cong, David Z. Pan, J. Cong, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes

David Z. Pan, Yier Jin, Kaveh Shamsi, 2019, IEEE Transactions on Information Forensics and Security.

Circuit Obfuscation and Oracle-guided Attacks: Who can Prevail?

Meng Li, David Z. Pan, Yier Jin, 2017, ACM Great Lakes Symposium on VLSI.

AppSAT: Approximately deobfuscating integrated circuits

Meng Li, David Z. Pan, Yier Jin, 2017, 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

TACO: temperature aware clock-tree optimization

David Z. Pan, Minsik Cho, Suhail Ahmed, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Design for manufacturability and reliability in extreme-scaling VLSI

David Z. Pan, Xiaoqing Xu, Bei Yu, 2016, Science China Information Sciences.

Electromigration-aware redundant via insertion

Jiwoo Pak, David Z. Pan, Bei Yu, 2015, The 20th Asia and South Pacific Design Automation Conference.

Electromigration Study for Multiscale Power/Ground Vias in TSV-Based 3-D ICs

Jiwoo Pak, Sung Kyu Lim, David Z. Pan, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Electromigration study for multi-scale power/ground vias in TSV-based 3D ICs

Jiwoo Pak, Sung Kyu Lim, David Z. Pan, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

TSV stress aware timing analysis with applications to 3D-IC layout optimization

Jae-Seok Yang, Sung Kyu Lim, David Z. Pan, 2010, Design Automation Conference.

Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures

David Z. Pan, Meng Li, Bei Yu, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

RoQNN: Noise-Aware Training for Robust Quantum Neural Networks pdf

David Z. Pan, Frederic T. Chong, Song Han, 2021, ArXiv.

Provably secure camouflaging strategy for IC protection

Meng Li, David Z. Pan, Yier Jin, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Multi-Scale High-Resolution Vision Transformer for Semantic Segmentation pdf

David Z. Pan, Dilin Wang, Hyoukjun Kwon, 2021, 2022 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR).

SqueezeLight: A Multi-Operand Ring-Based Optical Neural Network With Cross-Layer Scalability

Ray T. Chen, D. Pan, Jiaqi Gu, 2023, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Silicon photonic subspace neural chip for hardware-efficient deep learning pdf

David Z. Pan, Chenghao Feng, Zhoufeng Ying, 2021, ArXiv.

Electronic-photonic arithmetic logic unit for high-speed computing

Ray T. Chen, R. Soref, D. Pan, 2020, Nature Communications.

SHIELDeNN: Online Accelerated Framework for Fault-Tolerant Deep Neural Network Architectures

David Z. Pan, Navid Khoshavi, Yu Bi, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

L2ight: Enabling On-Chip Learning for Optical Neural Networks via Efficient in-situ Subspace Optimization pdf

David Z. Pan, Chenghao Feng, Zixuan Jiang, 2021, NeurIPS.

Toward Hardware-Efficient Optical Neural Networks: Beyond FFT Architecture via Joint Learnability

Ray T. Chen, David Z. Pan, Chenghao Feng, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

SqueezeLight: Towards Scalable Optical Neural Networks with Multi-Operand Ring Resonators

Ray T. Chen, David Z. Pan, Chenghao Feng, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

FLOPS: EFficient On-Chip Learning for OPtical Neural Networks Through Stochastic Zeroth-Order Optimization

Jiaqi Gu, Ray T. Chen, David Z. Pan, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

ROQ: A Noise-Aware Quantization Scheme Towards Robust Optical Neural Networks with Low-bit Controls

Jiaqi Gu, Ray T. Chen, David Z. Pan, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Towards Area-Efficient Optical Neural Networks: An FFT-based Architecture

Jiaqi Gu, Ray T. Chen, David Z. Pan, 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

Design Technology for Scalable and Robust Photonic Integrated Circuits: Invited Paper

Jiaqi Gu, Ray T. Chen, David Z. Pan, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Integrated multi-operand electro-optic logic gates for optical computing

Richard A. Soref, Ray T. Chen, David Z. Pan, 2019, Applied Physics Letters.

Hardware-software co-design of slimmed optical neural networks

Derong Liu, Meng Li, Ray T. Chen, 2019, ASP-DAC.

QOC: quantum on-chip training with parameter shift and gradient pruning

D. Pan, Yongshan Ding, Jiaqi Gu, 2022, DAC.

QuantumNAT: quantum noise-aware training with noise injection, quantization and normalization

D. Pan, Yongshan Ding, Jiaqi Gu, 2021, DAC.

Electronic-photonic arithmetic logic unit for high-speed computing

Jiaqi Gu, David Z. Pan, Chenghao Feng, 2020, Nature Communications.

Electro-Optic Ripple-Carry Adder in Integrated Silicon Photonics for Optical Computing

Richard A. Soref, Ray T. Chen, David Z. Pan, 2018, IEEE Journal of Selected Topics in Quantum Electronics.

Million-Channel Parallelism Fourier-Optic Convolutional Filter and Neural Network Processor

Puneet Gupta, Mario Miscuglio, Zibo Hu, 2020, 2020 Conference on Lasers and Electro-Optics (CLEO).

Design and experimental demonstration of a hardware-efficient integrated optical neural network

Ray T. Chen, D. Pan, Jiaqi Gu, 2022, Smart Photonic and Optoelectronic Integrated Circuits 2022.

Efficient On-Chip Learning for Optical Neural Networks Through Power-Aware Sparse Zeroth-Order Optimization

Ray T. Chen, David Z. Pan, Chenghao Feng, 2020, AAAI.

ADEPT: automatic differentiable DEsign of photonic tensor cores

Ray T. Chen, D. Pan, Jiaqi Gu, 2021, DAC.

Metal-Density-Driven Placement for CMP Variation and Routability

Yao-Wen Chang, David Z. Pan, Minsik Cho, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Toward High‐Speed and Energy‐Efficient Computing: A WDM‐Based Scalable On‐Chip Silicon Integrated Optical Comparator

Ray T. Chen, D. Pan, Jiaqi Gu, 2021, Laser & Photonics Reviews.

ELIAS: An Accurate and Extensible Lithography Aerial Image Simulator With Improved Numerical Algorithms

Peng Yu, D.Z. Pan, D. Pan, 2009, IEEE Transactions on Semiconductor Manufacturing.

DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks

David Z. Pan, Chandramouli V. Kashyap, Prateek Bhansali, 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).

MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper

Nan Sun, David Z. Pan, Shaolan Li, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Design for manufacturing meets advanced process control: A survey

David Z. Pan, Peng Yu, Minsik Cho, 2008, Journal of Process Control.

Lithography friendly routing: From construct-by-correction to correct-by-construction

David Z. Pan, D. Pan, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond

David Z. Pan, Minsik Cho, Minsik Cho, 2008, 2008 Asia and South Pacific Design Automation Conference.

Layout optimization algorithms for vlsi design and manufacturing

Gang Xu, David Z. Pan, Martin D. F. Wong, 2007 .

Lithography-aware physical design

D.Z. Pan, D. Pan, 2005, 2005 6th International Conference on ASIC.

RADAR: RET-aware detailed routing using fast lithography simulations

David Z. Pan, Joydeep Mitra, Peng Yu, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Manufacturability-aware physical layout optimizations

Martin D. F. Wong, D.Z. Pan, M.D.F. Wong, 2005, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..

High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints

Bei Yu, David Z. Pan, Yibo Lin, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A novel unified dummy fill insertion framework with SQP-based optimization method

Xuan Zeng, David Z. Pan, Changhao Yan, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

High performance dummy fill insertion with coupling and uniformity constraints

D. Pan, Yibo Lin, Bei Yu, 2017, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

On-chip QNN: Towards Efficient On-Chip Training of Quantum Neural Networks

Song Han, D. Pan, Yongshan Ding, 2022, ArXiv.

LithoGAN: End-to-End Lithography Modeling with Generative Adversarial Networks

David Z. Pan, Mohamed Baker Alawieh, Wei Ye, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Litho-GPA: Gaussian Process Assurance for Lithography Hotspot Detection

Meng Li, David Z. Pan, Mohamed Baker Alawieh, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

LithoROC: lithography hotspot detection with explicit ROC optimization

Qiang Liu, Meng Li, David Z. Pan, 2019, ASP-DAC.

A new lithography hotspot detection framework based on AdaBoost classifier and simplified feature extraction

David Z. Pan, Tetsuaki Matsunawa, Jhih-Rong Gao, 2015, Advanced Lithography.

Lithography hotspot detection and mitigation in nanometer VLSI

David Z. Pan, Bei Yu, Jhih-Rong Gao, 2013, 2013 IEEE 10th International Conference on ASIC.

High Performance Lithography Hotspot Detection With Successively Refined Pattern Identifications and Machine Learning

J. Andres Torres, David Z. Pan, Duo Ding, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

HEAT: Hardware-Efficient Automatic Tensor Decomposition for Transformer Compression

Anima Anandkumar, Jean Kossaifi, Ben Keller, 2022, ArXiv.

Mixed Precision Neural Architecture Search for Energy Efficient Deep Learning

Qiang Liu, David Z. Pan, Dilin Wang, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks

Nan Sun, David Z. Pan, Mingjie Liu, 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).

Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization

David Z. Pan, Brucek Khailany, Haoxing Ren, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

TAG: Learning Circuit Spatial Embedding From Layouts

Walker J. Turner, D. Pan, Keren Zhu, 2022, 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Cyclic Obfuscation for Creating SAT-Unresolvable Circuits

Meng Li, David Z. Pan, Yier Jin, 2017, ACM Great Lakes Symposium on VLSI.

Robust chip-level clock tree synthesis for SOC designs

David Z. Pan, Anand Rajaram, D. Pan, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Synthesis of variation tolerant clock distribution networks

David Z. Pan, Anand Rajaram, D. Pan, 2008 .

Manufacturability-Aware Routing

David Z. Pan, Joydeep Mitra, Minsik Cho, 2008, Handbook of Algorithms for Physical Design Automation.

BoxRouter 2.0: architecture and implementation of a hybrid and robust global router

Minsik Cho, D. Pan, Kun Yuan, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography

Hai Zhou, Xuan Zeng, David Z. Pan, 2015, ACM Trans. Design Autom. Electr. Syst..

OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture

David Z. Pan, Duo Ding, D. Pan, 2009, SLIP '09.

Incremental layer assignment for critical path timing

Derong Liu, David Z. Pan, Bei Yu, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

TILA: Timing-driven incremental layer assignment

Derong Liu, David Z. Pan, Bei Yu, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Optical proximity correction with hierarchical Bayes model

David Z. Pan, Tetsuaki Matsunawa, Bei Yu, 2015, Advanced Lithography.

Incremental Layer Assignment for Timing Optimization

Derong Liu, David Z. Pan, Bei Yu, 2017, ACM Trans. Design Autom. Electr. Syst..

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

Jiaqi Gu, David Z. Pan, Brucek Khailany, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Powernet: SOI Lateral Power Device Breakdown Prediction With Deep Neural Networks

David Z. Pan, Mohamed Baker Alawieh, Yibo Lin, 2020, IEEE Access.

Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks

David Z. Pan, Yibo Lin, Mingjie Liu, 2021, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).

GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance

Nan Sun, David Z. Pan, Shaolan Li, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Tackling signal electromigration with learning-based detection and multistage mitigation

David Z. Pan, Mohamed Baker Alawieh, Wei Ye, 2019, ASP-DAC.

Practical public PUF enabled by solving max-flow problem on chip

Meng Li, David Z. Pan, Kai Zhong, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Logic synthesis for energy-efficient photonic integrated circuits

Ray T. Chen, David Z. Pan, Zheng Zhao, 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

Track Routing and Optimization for Yield

David Z. Pan, Minsik Cho, Ruchir Puri, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Pushing ASIC performance in a power envelope

Dennis Sylvester, John M. Cohn, David Z. Pan, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

A practical split manufacturing framework for Trojan prevention via simultaneous wire lifting and cell insertion

Meng Li, David Z. Pan, Xiaoqing Xu, 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

Silicon microdisk-based full adders for optical computing.

Ray T. Chen, Richard Soref, Zheng Wang, 2018, Optics letters.

Automated logic synthesis for electro-optic logic-based integrated optical computing.

Ray T. Chen, Richard Soref, Chenghao Feng, 2018, Optics express.

TEMPO: Fast Mask Topography Effect Modeling with Deep Learning

Shigeki Nojima, David Z. Pan, Mohamed Baker Alawieh, 2020, ISPD.

Sequential Logic and Pipelining in Chip-Based Electronic-Photonic Digital Computing

Jiaqi Gu, Ray T. Chen, David Z. Pan, 2020, IEEE Photonics Journal.

Analysis of Microresonator-Based Logic Gate for High-Speed Optical Computing in Integrated Photonics

Ray T. Chen, David Z. Pan, Chenghao Feng, 2020, IEEE Journal of Selected Topics in Quantum Electronics.

Automated logic synthesis for electro-optic computing in integrated photonics

Ray T. Chen, David Z. Pan, Chenghao Feng, 2019, OPTO.

IcySAT: Improved SAT-based Attacks on Cyclic Locked Circuits

David Z. Pan, Yier Jin, Kaveh Shamsi, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Directed self-assembly for advanced chips

David Z. Pan, D. Pan, 2018, Nature Electronics.

Domain Wall-Magnetic Tunnel Junction Analog Content Addressable Memory Using Current and Projected Data

D. Pan, Keren Zhu, J. Incorvia, 2023, 2301.04598.

Process, design rule, and layout co-optimization for DSA based patterning of sub-10nm Finfet devices

David Z. Pan, Joydeep Mitra, Andres Torres, 2017, Advanced Lithography.

DREAMPlace 3.0: Multi-Electrostatics Based Robust VLSI Placement with Region Constraints

David Z. Pan, Jiaqi Gu, Yibo Lin, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs

David Z. Pan, Brucek Khailany, Yibo Lin, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

DREAMPIace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

David Z. Pan, Brucek Khailany, Yibo Lin, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips

David Z. Pan, Minsik Cho, Minsik Cho, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part II–Experimental Results and Impacts on Device Variability

Ru Huang, David Z. Pan, Xiaobo Jiang, 2013, IEEE Transactions on Electron Devices.

Layout Decomposition for Triple Patterning Lithography

Kun Yuan, David Z. Pan, Duo Ding, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Diffusion-Based Placement Migration With Application on Legalization

David Z. Pan, Gi-Joon Nam, Charles J. Alpert, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Latch Modeling for Statistical Timing Analysis

David Z. Pan, Anand Ramalingam, Sean X. Shi, 2008, 2008 Design, Automation and Test in Europe.

Pre-RMSNorm and Pre-CRMSNorm Transformers: Equivalent and Efficient Pre-LN Transformers

D. Pan, Jiaqi Gu, Hanqing Zhu, 2023, arXiv.org.

Modeling of Layout Aware Line-Edge Roughness and Poly Optimization for Leakage Minimization

David Z. Pan, Yongchan Ban, D. Pan, 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Electrical impact of line-edge roughness on sub-45nm node standard cell

Rajendran Panda, Savithri Sundareswaran, Yongchan Ban, 2009, Advanced Lithography.

Through-silicon-via material property variation impact on full-chip reliability and timing

S. Lim, Moongon Jung, D. Pan, 2014, IEEE International Interconnect Technology Conference.

Multilevel global placement with congestion control

Jason Cong, David Z. Pan, Xin Yuan, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Physical hierarchy generation with routing congestion control

Jason Cong, David Z. Pan, Chin-Chih Chang, 2002, ISPD '02.

ADAPT: An Adaptive Machine Learning Framework with Application to Lithography Hotspot Detection

D. Pan, M. Alawieh, 2021, 2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD).

MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC

D. Pan, Nan Sun, Keren Zhu, 2021, 2021 IEEE Custom Integrated Circuits Conference (CICC).

Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis

David Z. Pan, Biying Xu, Xiyuan Tang, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

Laplacian eigenmaps- and Bayesian clustering-based layout pattern sampling and its applications to hotspot detection and optical proximity correction

David Z. Pan, Tetsuaki Matsunawa, Bei Yu, 2016 .

Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits

Hao Chen, David Z. Pan, Xiyuan Tang, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII

Hao Chen, David Z. Pan, Shaolan Li, 2020, IEEE Design & Test.

Microdisk-Based Full Adders for Optical Computing in Silicon Photonics

Ray T. Chen, David Z. Pan, Richard Soref, 2018, 2018 Conference on Lasers and Electro-Optics (CLEO).

Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown

David Z. Pan, Subhendu Roy, D. Pan, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

Controlling NBTI degradation during static burn-in testing

David Z. Pan, Ashutosh Chakraborty, D. Pan, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Interconnect sizing and spacing with consideration of couplingcapacitance

Jason Cong, Cheng-Kok Koh, Lei He, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

QuantumNAT: quantum noise-aware training with noise injection, quantization and normalization

D. Pan, Yongshan Ding, Jiaqi Gu, 2021, DAC.

ELight: Toward Efficient and Aging-Resilient Photonic In-Memory Neurocomputing

Ray T. Chen, D. Pan, Jiaqi Gu, 2023, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

ELight: Enabling Efficient Photonic In-Memory Neurocomputing with Life Enhancement pdf

David Z. Pan, Chenghao Feng, Zixuan Jiang, 2021, 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC).

An Efficient Training Framework for Reversible Neural Architectures

Jiaqi Gu, David Z. Pan, Zixuan Jiang, 2020, ECCV.

Machine Learning in Physical Verification, Mask Synthesis, and Physical Design

David Z. Pan, Yibo Lin, D. Pan, 2019, Machine Learning in VLSI Computer-Aided Design.

EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation

David Z. Pan, Joydeep Ghosh, Duo Ding, 2012, 17th Asia and South Pacific Design Automation Conference.

Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection

Shigeki Nojima, Meng Li, David Z. Pan, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Generative Learning in VLSI Design for Manufacturability: Current Status and Future Directions

David Z. Pan, Mohamed Baker Alawieh, Yibo Lin, 2019, Journal of Microelectronic Manufacturing.

Layout decomposition for quadruple patterning lithography and beyond

David Z. Pan, Bei Yu, D. Pan, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Layout Decomposition for Other Patterning Techniques

Bei Yu, David Z. Pan, D. Pan, 2016 .

Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs

Jiwoo Pak, Sung Kyu Lim, David Z. Pan, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC

Xi Liu, Sung Kyu Lim, David Z. Pan, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A fast simulation framework for full-chip thermo-mechanical stress and reliability analysis of through-silicon-via based 3D ICs

David Z. Pan, Moongon Jung, Suk-Kyu Ryu, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC

Sung Kyu Lim, David Z. Pan, Moongon Jung, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Machine learning and pattern matching in physical design

Xuan Zeng, David Z. Pan, Tetsuaki Matsunawa, 2015, The 20th Asia and South Pacific Design Automation Conference.

Challenges and Approaches in VLSI Routing

Evangeline F. Y. Young, D. Pan, Yih-Lang Li, 2022, ISPD.

OSFA: A new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions

Derong Liu, David Z. Pan, Subhendu Roy, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Total power optimization combining placement, sizing and multi-Vt through slack distribution management

David Z. Pan, Tao Luo, David Newmark, 2008, 2008 Asia and South Pacific Design Automation Conference.

Wafer Map Defect Patterns Classification using Deep Selective Learning

David Z. Pan, Mohamed Baker Alawieh, Duane Boning, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks

David Z. Pan, Anand Rajaram, D. Pan, 2008, 2008 Asia and South Pacific Design Automation Conference.

Toward metrics of design automation research impact

Andrew B. Kahng, David Z. Pan, Siddhartha Nath, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Toward Metrics of Design Automation Research Impact ( invited paper )

Andrew B. Kahng, David Z. Pan, Siddhartha Nath, 2015 .

Design for Manufacturing With Emerging Nanolithography

David Z. Pan, Jhih-Rong Gao, Bei Yu, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

IP Protection and Supply Chain Security through Logic Obfuscation

David Z. Pan, Yier Jin, Kaveh Shamsi, 2019, ACM Trans. Design Autom. Electr. Syst..

elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs

David Z. Pan, Yibo Lin, Wuxi Li, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Clock power minimization using structured latch templates and decision tree induction

David Z. Pan, Natarajan Viswanathan, Charles J. Alpert, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Provably Secure Camouflaging Strategy for IC Protection

Meng Li, David Z. Pan, Zheng Zhao, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

IC Camouflaging Optimization and Evaluation

Meng Li, David Z. Pan, D. Pan, 2020 .

Integrated WDM-Based Optical Comparator for High-Speed Computing

Jiaqi Gu, Ray T. Chen, David Z. Pan, 2020, 2020 Conference on Lasers and Electro-Optics (CLEO).

Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal Flow

D. Pan, Keren Zhu, Mingjie Liu, 2023, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits

D. Pan, Keren Zhu, Mingjie Liu, 2022, 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC).

Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow

Hao Chen, David Z. Pan, Xiyuan Tang, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

A Machine Learning Based Framework for Sub-Resolution Assist Feature Generation

Chikaaki Kodama, Toshiya Kotani, Shigeki Nojima, 2016, ISPD.

AENEID: A generic lithography-friendly detailed router based on post-RET data learning and hotspot detection

Kun Yuan, David Z. Pan, Jhih-Rong Gao, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

High performance lithographic hotspot detection using hierarchically refined machine learning

Fedor G. Pikus, David Z. Pan, Duo Ding, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning

David Z. Pan, Linxiao Shen, Xiyuan Tang, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

High-Definition Routing Congestion Prediction for Large-Scale FPGAs

David Z. Pan, Mohamed Baker Alawieh, Love Singhal, 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity

Nan Sun, David Z. Pan, Biying Xu, 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout

Nan Sun, David Z. Pan, Biying Xu, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

PADE: A high-performance placer with automatic datapath extraction and evaluation through high-dimensional data learning

David Z. Pan, Duo Ding, Samuel I. Ward, 2012, DAC Design Automation Conference 2012.

Keep it straight: teaching placement how to better handle designs with datapaths

Earl E. Swartzlander, David Z. Pan, Natarajan Viswanathan, 2012, ISPD '12.

BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability

Kun Yuan, David Z. Pan, Minsik Cho, 2009, TODE.

BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP

David Z. Pan, Minsik Cho, Minsik Cho, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Wire Density Driven Global Routing for CMP Variation and Timing

Minsik Cho, D.Z. Pan, Hua Xiang, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs

Sung Kyu Lim, David Z. Pan, Moongon Jung, 2012, DAC Design Automation Conference 2012.

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization

David Pan, Miguel Gandara, Ahmet Budak, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier

Shaolan Li, Linxiao Shen, Wenda Zhao, 2020, IEEE Journal of Solid-State Circuits.

MOSAIC: Mask optimizing solution with process window aware inverse correction

David Z. Pan, Xiaoqing Xu, Jhih-Rong Gao, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Layout-dependent aging mitigation for critical path timing

Meng Li, David Z. Pan, Xiaoqing Xu, 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies

C. T. Gray, Walker J. Turner, B. Zimmer, 2022, ISPD.

Interactive Analog Layout Editing With Instant Placement and Routing Legalization

Runsheng Wang, D. Pan, Yibo Lin, 2023, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Interactive Analog Layout Editing with Instant Placement Legalization

David Z. Pan, Yibo Lin, Mingjie Liu, 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).

Device Layer-Aware Analytical Placement for Analog Circuits

Nan Sun, Derong Liu, David Z. Pan, 2019, ISPD.

9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier

Nan Sun, David Z. Pan, Wei Shi, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist

David Z. Pan, Yier Jin, Yibo Lin, 2020, 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

An In-Memory-Computing Charge-Domain Ternary CNN Classifier

Nan Sun, David Z. Pan, Jaydeep P. Kulkarni, 2021, 2021 IEEE Custom Integrated Circuits Conference (CICC).

A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier

Nan Sun, David Z. Pan, Wei Shi, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

TorchQuantum Case Study for Robust Quantum Circuits

Yiyu Shi, D. Pan, Yongshan Ding, 2022, International Conference on Computer Aided Design.

A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure

Nan Sun, David Z. Pan, Shaolan Li, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

A scaling compatible, synthesis friendly VCO-based delta-sigma ADC design and synthesis methodology

Nan Sun, David Z. Pan, Biying Xu, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Cross-Lock: Dense Layout-Level Interconnect Locking using Cross-bar Architectures

Meng Li, David Z. Pan, Yier Jin, 2018, ACM Great Lakes Symposium on VLSI.

TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing

Ulf Schlichtmann, David Z. Pan, Grace Li Zhang, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs

R. Puri, D. Pan, M. Choudhury, 2016, The 20th Asia and South Pacific Design Automation Conference.

Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs

David Z. Pan, Ruchir Puri, Subhendu Roy, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

KC2: Key-Condition Crunching for Fast Sequential Circuit Deobfuscation

Meng Li, David Z. Pan, Yier Jin, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Revisit sequential logic obfuscation: Attacks and defenses

David Z. Pan, Shaojie Zhang, Yier Jin, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits

Nan Sun, David Z. Pan, Xiaoqing Xu, 2017, ISPD.

A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure

Nan Sun, David Z. Pan, Shaolan Li, 2018, IEEE Journal of Solid-State Circuits.

Re-examining VLSI Manufacturing and Yield through the Lens of Deep Learning : (Invited Talk)

David Z. Pan, Mohamed Baker Alawieh, Wei Ye, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library

Nan Sun, David Z. Pan, Shaolan Li, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

ELIAD: Efficient Lithography Aware Detailed Routing Algorithm With Compact and Macro Post-OPC Printability Prediction

Kun Yuan, David Z. Pan, Yongchan Ban, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Fast Lithography Image Simulation By Exploiting Symmetries in Lithography Systems

Peng Yu, D.Z. Pan, Weifeng Qiu, 2008, IEEE Transactions on Semiconductor Manufacturing.

A novel intensity based optical proximity correction algorithm with speedup in lithography simulation

YU Peng, D. Pan, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

True process variation aware optical proximity correction with variational lithography modeling and model calibration

David Z. Pan, Sean X. Shi, Peng Yu, 2007 .

Process variation aware OPC with variational lithography modeling

David Z. Pan, Peng Yu, Sean X. Shi, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Fast lithography simulation under focus variations for OPC and layout optimizations

David Z. Pan, Chris A. Mack, Peng Yu, 2006, SPIE Advanced Lithography.

Practical Split Manufacturing Optimization

Meng Li, David Z. Pan, D. Pan, 2020 .

A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion

Bei Yu, David Z. Pan, Xiaoqing Xu, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction

YU Peng, D. Pan, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

Rethinking Sparsity in Performance Modeling for Analog and Mixed Circuits using Spike and Slab Models

David Z. Pan, Mohamed Baker Alawieh, Sinead Williamson, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

NormSoftmax: Normalizing the Input of Softmax to Accelerate and Stabilize Training

D. Pan, Jiaqi Gu, Zixuan Jiang, 2023, 2023 IEEE International Conference on Omni-layer Intelligent Systems (COINS).

Placement mitigation techniques for power grid electromigration

David Z. Pan, Xiaoqing Xu, Yongsheng Sun, 2017, 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Layout compliance for triple patterning lithography: an iterative approach

Bei Yu, David Z. Pan, Gilda Garreton, 2014, Photomask Technology.

Triple patterning lithography layout decomposition using end-cutting

D. Pan, Bei Yu, Jhih-Rong Gao, 2014 .

Layout Decomposition for Triple Patterning

David Z. Pan, Bei Yu, D. Pan, 2016, Encyclopedia of Algorithms.

Fully Integrated 20 Gbit/s Silicon Optical Computing Chip for 4-Bit Full Adders

Ray T. Chen, David Z. Pan, Chenghao Feng, 2019, 2019 IEEE Photonics Conference (IPC).

An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation

Hai Zhou, Xuan Zeng, David Z. Pan, 2017, ACM Trans. Design Autom. Electr. Syst..

Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues

Sani R. Nassif, Keith A. Bowman, David Z. Pan, 2012, 17th Asia and South Pacific Design Automation Conference.

TROY: Track Router with Yield-driven Wire Planning

David Z. Pan, Minsik Cho, Ruchir Puri, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Redundant-via enhanced maze routing for yield improvement

Li-Da Huang, Martin D. F. Wong, Gang Xu, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Manufacturability Aware Routing in Nanometer VLSI

David Z. Pan, Minsik Cho, Kun Yuan, 2010, Found. Trends Electron. Des. Autom..

Redundant Local-Loop Insertion for Unidirectional Routing

David Z. Pan, Xiaoqing Xu, Brian Cline, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Interconnect-Driven Floorplanning with Fast Global Wiring Planning and Optimization

Jason Cong, Xin Yuan, David Z. Pan, 2001 .

GAN-SRAF: Subresolution Assist Feature Generation Using Generative Adversarial Networks

David Z. Pan, Mohamed Baker Alawieh, Meng Li, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

SoulNet: ultrafast optical source optimization utilizing generative neural networks for advanced lithography

Yayi Wei, David Z. Pan, Lisong Dong, 2019, Journal of Micro/Nanolithography, MEMS, and MOEMS.

GAN-SRAF: Sub-Resolution Assist Feature Generation Using Conditional Generative Adversarial Networks

Meng Li, David Z. Pan, Qi-Xing Huang, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

LithoGAN

D. Pan, Yibo Lin, Wei Ye, 2019, Proceedings of the 56th Annual Design Automation Conference 2019.

Design for manufacturability and reliability in extreme-scaling VLSI

D. Pan, Yibo Lin, Xiaoqing Xu, 2016, Science China Information Sciences.

Subresolution Assist Feature Generation With Supervised Data Learning

Chikaaki Kodama, Toshiya Kotani, Shigeki Nojima, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method

Xuan Zeng, David Z. Pan, Hengliang Zhu, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Toward Unidirectional Routing Closure in Advanced Technology Nodes

David Z. Pan, Xiaoqing Xu, D. Pan, 2017, IPSJ Trans. Syst. LSI Des. Methodol..

Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis

David Z. Pan, Jian Chen, Anand Rajaram, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Simultaneous statistical delay and slew optimization for interconnect pipelines

David Z. Pan, Andrew Havlir, D. Pan, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Accurate thermal analysis considering nonlinear thermal conductivity

Sani R. Nassif, David Z. Pan, Anand Ramalingam, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Fast incremental link insertion in clock networks for skew variability reduction

David Z. Pan, Anand Rajaram, D. Pan, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Integrated multi-operand optical neurons for scalable and hardware-efficient deep learning

Ray T. Chen, D. Pan, Chenghao Feng, 2023, Nanophotonics.

M3ICRO: Machine Learning-Enabled Compact Photonic Tensor Core based on PRogrammable Multi-Operand Multimode Interference

Ray T. Chen, D. Pan, Jiaqi Gu, 2023, APL Machine Learning.

Sensitivity guided net weighting for placement-driven synthesis

David Z. Pan, Haoxing Ren, David S. Kung, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Timing-Driven Placement

David Z. Pan, Haoxing Ren, Bill Halpin, 2008, Handbook of Algorithms for Physical Design Automation.

Improved crosstalk modeling for noise constrained interconnect optimization

P. V. Srinivas, J. Cong, D. Pan, 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

Partial Functional Manipulation Based Wirelength Minimization

David Z. Pan, Avijit Dutta, D. Pan, 2006, 2006 International Conference on Computer Design.

Design for manufacturability and reliability for TSV-based 3D ICs

Jae-Seok Yang, Jiwoo Pak, Sung Kyu Lim, 2012, 17th Asia and South Pacific Design Automation Conference.

Directed self-assembly cut mask assignment for unidirectional design

David Z. Pan, Jhih-Rong Gao, Bei Yu, 2015 .

Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design

David Z. Pan, Jhih-Rong Gao, Bei Yu, 2015, ACM Great Lakes Symposium on VLSI.

Computational geometry based placement migration

David Z. Pan, Charles J. Alpert, Tao Luo, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing pdf

Ulf Schlichtmann, David Z. Pan, Bei Yu, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

TimingSAT: Decamouflaging Timing-based Logic Obfuscation

Meng Li, David Z. Pan, Yier Jin, 2018, 2018 IEEE International Test Conference (ITC).

An In-Memory-Computing Charge-Domain Ternary CNN Classifier

J. Kulkarni, Yongpan Liu, N. Lu, 2023, IEEE Journal of Solid-State Circuits.

Accurate power grid analysis with behavioral transistor network modeling

David Z. Pan, Anand Ramalingam, Giri Devarayanadurg, 2007, ISPD '07.