Hao-Jan Chao

A circular pipeline processing based deterministic parallel test pattern generator

Jiun-Lang Huang, Laung-Terng Wang, Kuen-Wei Yeh, 2013, 2013 IEEE International Test Conference (ITC).

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains

Wen-Ben Jone, Shianling Wu, Xiaoqing Wen, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains

Nur A. Touba, Fangfang Li, Wen-Ben Jone, 2010, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems.

Logic BIST Architecture for System-Level Test and Diagnosis

Shianling Wu, Yuan Zuo, Xingang Wang, 2009, 2009 Asian Test Symposium.

Physical-design-friendly hierarchical logic built-in self-test—A case study

Shianling Wu, Jun Wu, Laung-Terng Wang, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

to detect multiple-capture dft system or retrieve from border clock domain errors during the self-test or scan-test

Hao-Jan Chao, Po-Ching Hsu, Shih-Chia F Kien-Kwo S. Road Kao, 2002 .

Turbo1500: Core-Based Design for Test and Diagnosis

Fangfang Li, Wen-Ben Jone, Shianling Wu, 2009, IEEE Design & Test of Computers.

Practical Challenges in Logic BIST Implementation – Case Studies

Shianling Wu, Hiroshi Furukawa, Laung-Terng Wang, 2008, 2008 17th Asian Test Symposium.

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard

Fangfang Li, Wen-Ben Jone, Shianling Wu, 2008, 2008 IEEE International Test Conference.

A method and apparatus for diagnosing failures in an integrated circuit using techniques of the type design-for-debug (DFD)

Hsin-Po Wang, Hao-Jan Chao, Shyh-Horng Lin, 2002 .