A. Wu

发表

TRACER-fpga: a router for RAM-based FPGA's

Youn-Long Lin, Allen C.-H. Wu, Ching-Dong Chen, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Multi-way Fpga Partitioning By Fully Exploiting Design Hierarchy

A. Wu, Wen-Jong Fang, 1997, Proceedings of the 34th Design Automation Conference.

Youn-Long Steve Lin

Nikil D. Dutt, Daniel Gajski, Allen C.-H. Wu, 1992 .

A timing-driven soft-macro resynthesis method in interaction with chip floorplanning

A. Wu, Y. Lin, Hsiao-Pin Su, 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

Guest editorial 11th international symposium on system-level synthesis and design (ISSS'98)

Nikil D. Dutt, Allen C.-H. Wu, N. Dutt, 2000, IEEE Trans. Very Large Scale Integr. Syst..

A Performance and Routability Driven Router for FPGAs Considering Path Delays

Allen C.-H. Wu, Yuh-Sheng Lee, Yuh-Sheng Lee, 1995, 32nd Design Automation Conference.

Timing models for high-level synthesis

Viraphol Chaiyakul, Daniel Gajski, Allen C.-H. Wu, 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

Essential issues for IP reuse

V. Chaiyakul, D.D. Gajski, A.C.-H. Wu, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

Embedded tutorial: essential issues for IP reuse

Daniel D. Gajski, Viraphol Chaiyakul, Allen C.-H. Wu, 2000, ASP-DAC '00.

A transformation-based method for loop folding

Daniel Gajski, Youn-Long Lin, Allen C.-H. Wu, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliers

Allen C.-H. Wu, Alex C.-Y. Chang, M.-J. Liao, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

A predictive system shutdown method for energy saving of event-driven computation

Allen C.-H. Wu, Chi-Hong Hwang, A. Wu, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

High ― Level Synthesis: Introduction to Chip and System Design

Daniel D. Gajski, Nikil Dutt, Allen C.-H. Wu, 1992 .

An RTL design-space exploration method for high-level applications

Peng-Cheng Kao, Chih-Kuang Hsieh, A.C.-H. Wu, 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

A new algorithm for transistor sizing in CMOS circuits

Daniel Gajski, Allen C.-H. Wu, Nels Vander Zanden, 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

An effective methodology for functional pipelining

Daniel D. Gajski, Youn-Long Lin, Allen C.-H. Wu, 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

Scheduling techniques for variable voltage low power designs

Allen C.-H. Wu, Cheng-Tsung Hwang, Yann-Rue Lin, 1997, TODE.

EmGen-a module generator for logic emulation applications

Duan-Ping Chen, Wen-Jong Fang, Allen C.-H. Wu, 1999, IEEE Trans. Very Large Scale Integr. Syst..

Accurate layout area and delay modeling for system level design

V. Chaiyakul, C. Ramachandran, F. J. Kurdahi, 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

An efficient multi-view design model for real-time interactive synthesis

Daniel D. Gajski, Tedd Hadley, Allen C.-H. Wu, 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations

Wen-Jong Fang, Allen C.-H. Wu, A. Wu, 1996, Proceedings of International Conference on Computer Aided Design.

A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning

Youn-Long Lin, Allen C.-H. Wu, Hsiao-Pin Su, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy

Youn-Long Lin, Allen C.-H. Wu, Hsiao-Pin Su, 1998, ISPD '98.

A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations

Wen-Jong Fang, Allen C.-H. Wu, A. Wu, 1996, Proceedings of International Conference on Computer Aided Design.

Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs

Wen-Jong Fang, Allen C.-H. Wu, A. Wu, 1998, IEEE Des. Test Comput..

A Real-time Rtl Engineering-change Method Supporting On-line Debugging For Logic-emulation Applications

Wen-Jong Fang, Ti-Yen Yen, A. Wu, 1997, Proceedings of the 34th Design Automation Conference.

Module generation of complex macros for logic-emulation applications

Duan-Ping Chen, Wen-Jong Fang, Allen C.-H. Wu, 1997, FPGA '97.

DP-Gen: a datapath generator for multiple-FPGA applications

Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Multiway FPGA partitioning by fully exploiting design hierarchy

A. Wu, Wen-Jong Fang, 2000, TODE.

A Novel Privacy-Preserving Deep Learning Scheme without Using Cryptography Component pdf

TingTing Hwang, Allen C.-H. Wu, Chin-Yu Sun, 2019, ArXiv.

Performance-Driven Crosstalk Elimination at Postcompiler Level—The Case of Low-Crosstalk Op-Code Assignment

TingTing Hwang, Allen C.-H. Wu, Wu-An Kuo, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Decomposition of instruction decoder for low power designs

TingTing Hwang, Allen C.-H. Wu, Wu-An Kuo, 2006, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)..

Performance-driven crosstalk elimination at post-compiler level

TingTing Hwang, Allen C.-H. Wu, Wu-An Kuo, 2006, 2006 IEEE International Symposium on Circuits and Systems.

High ― Level Synthesis: Introduction to Chip and System Design

D. Gajski, N. Dutt, A. Wu, 1992 .