Yi Li

A 691 Mbps 1.392mm2 configurable radix-16 turbo decoder ASIC for 3GPP-LTE and WiMAX systems in 65nm CMOS

Yi Li, Xiaoyang Zeng, Yun Chen, 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Multilevel Phase Analysis

Yi Li, Haibo Chen, Jiaxin Li, 2015, TECS.

Recurrent Memory Reasoning Network for Expert Finding in Community Question Answering

Xuanjing Huang, Jinlan Fu, Yu-Gang Jiang, 2020, WSDM.

Parallelizing image feature extraction algorithms on multi-core platforms

Yi Li, Haibo Chen, Bo Song, 2016, J. Parallel Distributed Comput..

A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array

Yi Li, Jie Lin, Jiajie Zhang, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

On t-Closeness with KL-Divergence and Semantic Privacy

Yi Li, Aoying Zhou, Chaofeng Sha, 2010, DASFAA.

Improving dynamic prediction accuracy through multi-level phase analysis

Yi Li, Zhenman Fang, Haibo Chen, 2012, LCTES '12.

Parallelized Race Detection Based on GPU Architecture

Yi Li, Zheng Zhang, Weihua Zhang, 2014, ACA.