Stephen Jang

SAT-Based Logic Optimization and Resynthesis

R. Brayton, A. Mishchenko, J. H. Jiang, 2007 .

A Power Optimization Toolbox for Logic Synthesis and Mapping

R. Brayton, K. Chung, A. Mishchenko, 2009 .

Scalable and scalably-verifiable sequential synthesis

Michael L. Case, R. Brayton, A. Mishchenko, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Scalable don't-care-based logic optimization and resynthesis

R. Brayton, A. Mishchenko, J. H. Jiang, 2011, TRETS.

SAT-Based Logic Optimization and Resynthesis

R. Brayton, A. Mishchenko, J. H. Jiang, 2007 .

WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging

Alan Mishchenko, Stephen Jang, Kevin Chung, 2009, TRETS.

Scalable don't-care-based logic optimization and resynthesis

Robert K. Brayton, Jie-Hong Roland Jiang, Alan Mishchenko, 2009, FPGA '09.

WireMap: FPGA technology mapping for improved routability

Alan Mishchenko, Stephen Jang, Kevin Chung, 2008, FPGA '08.