D. Lin

I. Radu, B. Sorée, C. Huyghebaert, 2015, 2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM).

Shaping the future of nanoelectronics beyond the Si roadmap with new materials and devices

Geert Hellings, Jerome Mitard, Anne Vandooren, 2010, Advanced Lithography.

Reactive plasma cleaning and restoration of transition metal dichalcogenide monolayers

Kristof M. Bal, D. Lin, S. De Gendt, 2021, npj 2D Materials and Applications.

Engineering Wafer-Scale Epitaxial Two-Dimensional Materials through Sapphire Template Screening for Advanced High-Performance Nanoelectronics.

I. Radu, M. Caymax, C. Huyghebaert, 2021, ACS nano.

Modeling and Optimization of Plasmonic Detectors for Beyond-CMOS Plasmonic Majority Logic Gates

F. Catthoor, A. Naeemi, P. Van Dorpe, 2020, Journal of Lightwave Technology.

A flexible InGaAs nanomembrane PhotoFET with tunable responsivities in near- and short-wave IR region for lightweight imaging applications

D. Mocuta, A. Thean, N. Collaert, 2019, APL Materials.

Ultra-scaled MOCVD MoS2 MOSFETs with 42nm contact pitch and 250µA/µm drain current

I. Radu, M. Caymax, D. Lin, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Understanding the factors affecting contact resistance in nanowire field effect transistors (NWFETs) to improve nanoscale contacts for future scaling

H. Bender, N. Collaert, T. Ivanov, 2022, Journal of Applied Physics.

Amorphous Gadolinium Aluminate as a Dielectric and Sulfur for Indium Phosphide Passivation

O. Richard, T. Ivanov, C. Adelmann, 2019, ACS Applied Electronic Materials.

MoS2 Functionalization with a Sub-nm Thin SiO2 Layer for Atomic Layer Deposition of High-κ Dielectrics

H. Bender, I. Radu, M. Heyns, 2017 .

Defect formation in III–V fin grown by aspect ratio trapping technique: A first-principles study

N. Collaert, C. Merckling, N. Waldron, 2014, 2014 IEEE International Reliability Physics Symposium.

Beyond-Si materials and devices for more Moore and more than Moore applications

A. Vandooren, Anabela Veloso, Liesbeth Witters, 2016, 2016 International Conference on IC Design and Technology (ICICDT).

Comparative study of Au/Pd/Ni(P) surface finish in eutectic PbSn and Sn3Ag0.5Cu soldering systems

D. Lin, C. Ho, S. Peng, 2009, 2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference.

Top-down InGaAs nanowire and fin vertical FETs with record performance

H. Bender, A. Thean, N. Collaert, 2016, 2016 IEEE Symposium on VLSI Technology.

Border Traps in Ge/III–V Channel Devices: Analysis and Reliability Aspects

Cor Claeys, Eddy Simoen, C. Merckling, 2013, IEEE Transactions on Device and Materials Reliability.

Measurement of direct and indirect bandgaps in synthetic ultrathin MoS2 and WS2 films from photoconductivity spectra

I. Radu, A. Stesmans, M. Houssa, 2021 .

Germanium surface passivation and atomic layer deposition of high-k dielectrics—a tutorial review on Ge-based MOS capacitors

C. Detavernier, M. Caymax, Shao-Ren Deng, 2012 .

High-Performance Ge MOS Capacitors by $\hbox{O}_{2}$ Plasma Passivation and $\hbox{O}_{2}$ Ambient Annealing

C. Detavernier, M. Caymax, Qi Xie, 2011, IEEE Electron Device Letters.

Transport properties of chemically synthesized MoS2 – Dielectric effects and defects scattering

I. Radu, C. Huyghebaert, D. Lin, 2016 .

A New Quality Metric for III–V/High-k MOS Gate Stacks Based on the Frequency Dispersion of Accumulation Capacitance and the CET

A. Thean, N. Collaert, J. Franco, 2017, IEEE Electron Device Letters.

The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices

Aaron Thean, Philippe Roussel, Guido Groeseneken, 2015, 2015 IEEE International Reliability Physics Symposium.

Beyond interface: The impact of oxide border traps on InGaAs and Ge n-MOSFETs

R. Degraeve, D. Lin, N. Collaert, 2012, 2012 International Electron Devices Meeting.

TiO2/HfO2 Bi-Layer Gate Stacks Grown by Atomic Layer Deposition for Germanium-Based Metal-Oxide-Semiconductor Devices Using GeOxNy Passivation Layer

C. Detavernier, M. Caymax, S. V. D. Berghe, 2011 .

Density and Capture Cross-Section of Interface Traps in GeSnO2 and GeO2 Grown on Heteroepitaxial GeSn.

C. Merckling, R. Loo, M. Heyns, 2016, ACS applied materials & interfaces.

Impact of device scaling on the electrical properties of MoS2 field-effect transistors

I. Radu, M. Heyns, D. Lin, 2021, Scientific Reports.

Hf-based high-k dielectrics for p-Ge MOS gate stacks

M. Caymax, D. Lin, L. Nyns, 2014 .

Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab

T. Schram, K. Devriendt, I. Radu, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Dual gate synthetic WS2 MOSFETs with 120μS/μm Gm 2.7μF/cm2 capacitance and ambipolar channel

I. Radu, D. Lin, S. Sutar, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

A Deep Level Transient Spectroscopy Study of Hole Traps in GexSe1−x-based Layers for Ovonic Threshold Switching Selectors

G. Kar, A. Stesmans, E. Simoen, 2020 .

WS2 transistors on 300 mm wafers with BEOL compatibility

Cedric Huyghebaert, Tom Schram, Dennis Lin, 2017, 2017 47th European Solid-State Device Research Conference (ESSDERC).

Heterogeneous Integration and Fabrication of III-V MOS Devices in a 200mm Processing Environment

N. Waldron, M. Caymax, M. Heyns, 2011 .

MoS2/MoTe2 Heterostructure Tunnel FETs Using Gated Schottky Contacts

I. Radu, M. Luisier, G. Groeseneken, 2019, Advanced Functional Materials.

Tunneling transistors based on MoS2/MoTe2 Van der Waals heterostructures

Iuliana Radu, Guido Groeseneken, Cedric Huyghebaert, 2017, 2017 47th European Solid-State Device Research Conference (ESSDERC).

An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

C. Merckling, D. Lin, N. Waldron, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

The impact of the gate dielectric quality in developing Au-free D-mode and E-mode recessed gate AlGaN/GaN transistors on a 200mm Si substrate

Guido Groeseneken, Denis Marcon, Marleen Van Hove, 2015, 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD).

Record 47 mV/dec top-down vertical nanowire InGaAs/GaAsSb tunnel FETs

Nadine Collaert, Tsvetan Ivanov, Dennis Lin, 2018, 2018 IEEE Symposium on VLSI Technology.

InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature

D. Mocuta, A. Thean, N. Collaert, 2016 .

Record performance Top-down In0.53Ga0.47As vertical nanowire FETs and vertical nanosheets

N. Collaert, A. Veloso, T. Ivanov, 2017, International Electron Devices Meeting.

SiGe MEMS at processing temperatures below 250 °C

R. Puers, C. Hoof, S. Sedky, 2012 .

Laser annealed SiGe devices for MEMS applications at temperatures below 250°C

C. van Hoof, R. Puers, S. Sedky, 2011, 2011 16th International Solid-State Sensors, Actuators and Microsystems Conference.

FETs on 2-D Materials: Deconvolution of the Channel and Contact Characteristics by Four-Terminal Resistance Measurements on WSe2 Transistors

A. Thean, I. Radu, D. Lin, 2017, IEEE Transactions on Electron Devices.

Analysis of III–V oxides at high-k/InGaAs interfaces induced by metal electrodes

N. Collaert, D. Lin, Heiji Watanabe, 2019, Japanese Journal of Applied Physics.

Systematic study of interfacial reactions induced by metal electrodes in high-k/InGaAs gate stacks

A. Thean, N. Collaert, J. Franco, 2016 .

Density and Capture Cross-Section of Interface Traps in GeSnO2 and GeO2 Grown on Heteroepitaxial GeSn.

C. Merckling, R. Loo, M. Heyns, 2016, ACS applied materials & interfaces.

2D materials: roadmap to CMOS integration

C. Huyghebaert, A. Leonhardt, D. Lin, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).