Shinya Takamaeda-Yamazaki

发表

Smart Core System for Dependable Many-Core Processor with Multifunction Routers

Kenji Kise, Shimpei Sato, Takefumi Miyoshi, 2010, 2010 First International Conference on Networking and Computing.

Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions

Tetsuya Asai, Masayuki Ikebe, Masato Motomura, 2018, 2018 IEEE Visual Communications and Image Processing (VCIP).

Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators

Jun Yao, Yoshikazu Inagaki, Yasuhiko Nakashima, 2014, 2014 Second International Symposium on Computing and Networking.

An FPGA-based scalable simulation accelerator for tile architectures

Kenji Kise, Shinya Takamaeda-Yamazaki, Ryosuke Sasakawa, 2011, CARN.

A CGRA-Based Approach for Accelerating Convolutional Neural Networks

Jun Yao, Yasuhiko Nakashima, Shinya Takamaeda-Yamazaki, 2015, 2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip.

A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators

Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki, 2019, 2019 Seventh International Symposium on Computing and Networking (CANDAR).

Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA

Tetsuya Asai, Masayuki Ikebe, Hotaka Kusano, 2018, Microprocess. Microsystems.

Stop the World: A Lightweight Runtime Power-Capping Mechanism for FPGAs

Yasuhiko Nakashima, Shinya Takamaeda-Yamazaki, Keisuke Fujimoto, 2016, 2016 Fourth International Symposium on Computing and Networking (CANDAR).

ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs

Kenji Kise, Naoki Fujieda, Shinya Takamaeda-Yamazaki, 2012, ARC.

Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators

Tetsuya Asai, Kota Ando, Kodai Ueyoshi, 2018, 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC).

flipSyrup: Cycle-accurate hardware simulation framework on abstract FPGA platforms

Kenji Kise, Shinya Takamaeda-Yamazaki, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

DIVA-EMIN : Efficient Dependability for Post-Silicon Materials

Jun Yao, Shinya Takamaeda-Yamazaki, Oliver Kaltstein, 2014 .

A High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator

Tetsuya Asai, Masayuki Ikebe, Masato Motomura, 2017 .

Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing

Tetsuya Asai, Alexandre Schmid, Masayuki Ikebe, 2018, Complex..

Design Space Exploration of Computational Photography Accelerator (コンピュータシステム)

Shinya Takamaeda-Yamazaki, Yuttakon Yuttakonkit, Tran Thi Hong, 2015, ARC 2015.

A Tree-Based Checkpointing Architecture for the Dependability of FPGA Computing

Takashi Nakada, Yasuhiko Nakashima, Shinya Takamaeda-Yamazaki, 2018, IEICE Trans. Inf. Syst..

Logarithmic Compression for Memory Footprint Reduction in Neural Network Training

Tetsuya Asai, Kentaro Orimo, Kota Ando, 2017, 2017 Fifth International Symposium on Computing and Networking (CANDAR).

A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes

Tadahiro Kuroda, Kodai Ueyoshi, Kota Shiba, 2020, ISCAS.

Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration

Tetsuya Asai, Masayuki Ikebe, Masato Motomura, 2018, 2018 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

Accelerating deep learning by binarized hardware

Tetsuya Asai, Kota Ando, Kodai Ueyoshi, 2017, 2017 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC).

QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS

Tadahiro Kuroda, Tomoki Miyata, Kota Ando, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware

Tetsuya Asai, Kota Ando, Kodai Ueyoshi, 2018, 2018 International Conference on Field-Programmable Technology (FPT).

Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs

Masato Motomura, Atsuyoshi Nakamura, Shinya Takamaeda-Yamazaki, 2020, ARC.

Towards a Low-Power Accelerator of Many FPGAs for Stencil Computations

Kenji Kise, Shinya Takamaeda-Yamazaki, Ryohei Kobayashi, 2012, 2012 Third International Conference on Networking and Computing.

A Time-Division Multiplexing Ising Machine on FPGAs

Tetsuya Asai, Masayuki Ikebe, Masato Motomura, 2017, HEART.

CPRtree: A Tree-Based Checkpointing Architecture for Heterogeneous FPGA Computing

Yasuhiko Nakashima, Shinya Takamaeda-Yamazaki, Supasit Kajkamhaeng, 2016, 2016 Fourth International Symposium on Computing and Networking (CANDAR).

7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions

Masato Motomura, Hiroshi Teramoto, Shinya Takamaeda-Yamazaki, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A Multithreaded CGRA for Convolutional Neural Network Processing

Tetsuya Asai, Kota Ando, Masayuki Ikebe, 2017 .

CPRring: A Structure-Aware Ring-Based Checkpointing Architecture for FPGA Computing

Takashi Nakada, Yasuhiko Nakashima, Shinya Takamaeda-Yamazaki, 2017, 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

A Sutudy on a Comprehensive Architecture Exploration Environment for Emerging Applications

Jun Yao, Yasuhiko Nakashima, Shinya Takamaeda-Yamazaki, 2014 .

Performance Optimization of Light-Field Applications on GPU

Yasuhiko Nakashima, Shinya Takamaeda-Yamazaki, Yuttakon Yuttakonkit, 2016, IEICE Trans. Inf. Syst..

Performance evaluation of 802.11ah Viterbi decoder for IoT applications

Yasuhiko Nakashima, Thi Hong Tran, Shinya Takamaeda-Yamazaki, 2015, 2015 International Conference on Advanced Technologies for Communications (ATC).

DeltaNet: Differential Binary Neural Network

Tetsuya Asai, Kota Ando, Masato Motomura, 2019, 2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks

Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki, 2020, Int. J. Netw. Comput..

A framework for efficient rapid prototyping by virtually enlarging FPGA resources

Kenji Kise, Shinya Takamaeda-Yamazaki, 2014, 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14).

Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs

Kenji Kise, Yuichiro Tanaka, Shinya Takamaeda-Yamazaki, 2015, IEICE Trans. Inf. Syst..

Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL

Shinya Takamaeda-Yamazaki, Shinya Takamaeda-Yamazaki, 2015, ARC.

Ultrasmall: The smallest MIPS soft processor

Kenji Kise, Yuichiro Tanaka, Shinya Takamaeda-Yamazaki, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis

Yasuhiko Nakashima, Thi Hong Tran, Shinya Takamaeda-Yamazaki, 2016, 2016 Fourth International Symposium on Computing and Networking (CANDAR).

FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects

Tetsuya Asai, Alexandre Schmid, Masayuki Ikebe, 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

Multi-FPGA based Prototyping Framework for Emerging Manycores

Shinya Takamaeda-Yamazaki, 伸也高前田（山崎）, 2014 .

A Distributed Memory Based Embedded CGRA for Accelerating Stencil Computations

Yasuhiko Nakashima, Shinya Takamaeda-Yamazaki, Yuttakon Yuttakonkit, 2015, 2015 Third International Symposium on Computing and Networking (CANDAR).

Quantization Error-Based Regularization in Neural Networks

Tetsuya Asai, Kota Ando, Kodai Ueyoshi, 2017, SGAI Conf..

An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising

Shinya Takamaeda-Yamazaki, Nobuho Hashimoto, Shinya Takamaeda-Yamazaki, 2021, 2021 31st International Conference on Field-Programmable Logic and Applications (FPL).

ASBNN: Acceleration of Bayesian Convolutional Neural Networks by Algorithm-hardware Co-design

Shinya Takamaeda-Yamazaki, Yoshiki Fujiwara, 2021, 2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP).

Request Density Aware Fair Memory Scheduling

Shinya Takamaeda-Yamazaki, Takakazu Ikeda, 2012 .