P. Oldiges

发表

Modeling line edge roughness effects in sub 100 nanometer gate length devices

M. Ieong, K. Petrillo, M. Sanchez, 2000, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502).

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

L. H. Vanamurth, D. Yang, T. Adam, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Electrostatic analysis of carbon nanotube arrays

H. Wong, P. Oldiges, Xinlin Wang, 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

D. Corliss, T. Standaert, R. Wong, 2017, 2017 Symposium on VLSI Technology.

Toward Ultimate Scaling of MOSFET

J. Cai, D. Frank, R. Muralidhar, 2016, IEEE Transactions on Electron Devices.

FinFET design considerations based on 3-D simulation and analytical modeling

G. Pei, Edwin C. Kan, P. Oldiges, 2002 .

Controlling floating-body effects for 0.13 /spl mu/m and 0.10 /spl mu/m SOI CMOS

Rajiv V. Joshi, Ching-Te Chuang, P. Oldiges, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Examination of hole mobility in ultra-thin body SOI MOSFETs

M. Ieong, W. Haensch, T. Kanarsky, 2002, Digest. International Electron Devices Meeting,.

Low-Energy Proton-Induced Single-Event-Upsets in 65 nm Node, Silicon-on-Insulator, Latches and Memory Cells

H.H.K. Tang, M. Gordon, D. Heidel, 2007, IEEE Transactions on Nuclear Science.

Metal-Gate Granularity-Induced Threshold Voltage Variability and Mismatch in Si Gate-All-Around Nanowire n-MOSFETs

V. Rao, K. Murali, P. Oldiges, 2014, IEEE Transactions on Electron Devices.

Single-Event-Upset Critical Charge Measurements and Modeling of 65 nm Silicon-on-Insulator Latches and Memory Cells

P. Oldiges, C. Plettner, H.H.K. Tang, 2006, IEEE Transactions on Nuclear Science.

HOT-carrier degradation in undoped-body ETSOI FETS and SOI FINFETS

H. Jagannathan, J. Stathis, K. Cheng, 2010, 2010 IEEE International Reliability Physics Symposium.

Low Energy Proton SEUs in 32-nm SOI SRAMs at Low Vdd

K. Stawiasz, M. Gordon, M. Turowski, 2017, IEEE Transactions on Nuclear Science.

CMOS Logic Device and Circuit Performance of Si Gate All Around Nanowire MOSFET

Hiroshi Iwai, Kenji Natori, Mohit Bajaj, 2014, IEEE Transactions on Electron Devices.

Suppression of boron diffusion in deep submicron devices

M. Gribelyuk, P. Oldiges, P. Ronsheim, 2011 .

Strained SiGe/Ge Buried Channel pMOSFETs Design For High Performance Applications

M. Ieong, S. Koester, K. Rim, 2006, 2006 64th Device Research Conference.

Strained Si CMOS (SS CMOS) technology: Opportunities and challenges

Keith A. Jenkins, Byoung Hun Lee, P. Oldiges, 2003 .

Channel doping impact on FinFETs for 22nm and beyond

P. Oldiges, T. B. Hook, T. Yamashita, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Protecting Big Blue from Rogue Subatomic Particles

K. Muller, H.H.K. Tang, A. KleinOsowski, 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.

(Invited) Silicon Germanium FinFET Device Physics, Process Integration and Modeling Considerations

Pierre Morin, Ali Khakifirooz, Bruce B. Doris, 2014 .

Alpha-particle-induced upsets in advanced CMOS circuits and technology

David F. Heidel, Ethan H. Cannon, Phil Oldiges, 2008, IBM J. Res. Dev..

Crystallographic-Orientation-Dependent Gate-Induced Drain Leakage in Nanoscale MOSFETs

E. Nowak, S. Furkay, K. Murali, 2010, IEEE Transactions on Electron Devices.

Poly-Si/high-k gate stacks with near-ideal threshold voltage and mobility

P. Oldiges, K. Maitra, V. Narayanan, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

Meeting the Challenge of Multiple Threshold Voltages in Highly Scaled Undoped FinFETs

Jin Cai, P. Oldiges, I. Lauer, 2013, IEEE Transactions on Electron Devices.

Impact of heater configuration on Reset characteristics of PCM Mushroom cell

P. Oldiges, M. BrightSky, P. Adusumilli, 2019, 2019 IEEE Albany Nanotechnology Symposium (ANS).

Molecular dynamics simulations of LATID implants into silicon

P. Oldiges, K. Nordlund, Huilong Zhu, 1997, SISPAD '97. 1997 International Conference on Simulation of Semiconductor Processes and Devices. Technical Digest.

Simulation Study of Multiple FIN FinFET Design for 32nm Technology Node and Beyond

W. Haensch, P. Oldiges, O. Dokumaci, 2007 .

Simulation Study on Channel Length Scaling of High Performance Partially Depleted Metal Gate and Poly Gate SOI MOSFETs

S. Narasimha, R. Dennard, W. Haensch, 2006, 2006 International Conference on Simulation of Semiconductor Processes and Devices.

Examination of Spatial Frequency Dependence of Line Edge Roughness on MOS Device Characteristics

P. Oldiges, C. Murthy, 2004 .

A comparative study of fin-last and fin-first SOI FinFETs

Josephine B. Chang, M. Khare, W. Haensch, 2013, 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

D. Liu, P. Oldiges, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

B. Lherron, D. Chanemougame, P. Oldiges, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Impact of Mobile Charge on Matching Sensitivity in SOI Analog Circuits

W. Rausch, P. Oldiges, P. Ronsheim, 2007, 2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference.

Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond

Phil Oldiges, Terence Hook, Myung-Hee Na, 2015, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Vertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate

Jin Cai, P. Oldiges, Tak Ning, 2003, 2003 Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (IEEE Cat. No.03CH37440).

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

P. Oldiges, C. Park, N. Loubet, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond

Phil Oldiges, Wilfried Haensch, Andres Bryant, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Ab initio Study of Metal Grain Orientation-Dependent Work Function and its Impact on FinFET Variability

Stephen S. Furkay, Abhisek Dixit, Mohit Bajaj, 2013, IEEE Transactions on Electron Devices.

A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs

S. Narasimha, J. Johnson, M. Khare, 2015, Symposium on VLSI Technology.

Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT

Jie Yang, Terence B. Hook, Andreas Knorr, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Sub-25nm FinFET with advanced fin formation and short channel effect engineering

K. Maitra, P. Kulkarni, T. Yamashita, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Soft error rate modeling and analysis of SOI/TFT SRAM's

P. Oldiges, 1996, 1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095).

Theoretical determination of the temporal and spatial structure of /spl alpha/-particle induced electron-hole pair generation in silicon

R. Dennard, M. Ieong, D. F. Heidel, 2000 .

Investigation of Fixed Oxide Charge and Fin Profile Effects on Bulk FinFET Device Characteristics

T. Standaert, Xin Sun, D. Guo, 2013, IEEE Electron Device Letters.