K. Kai

Optimizing the DRAM refresh count for merged DRAM/logic LSIs

Kazuaki Murakami, Taku Ohsawa, Koji Kai, 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs

Kazuaki Murakami, Koji Inoue, Koji Kai, 2000 .

Dynamically variable line-size cache exploiting high on-chip memory bandwidth of merged DRAM/logic LSIs

Kazuaki Murakami, Koji Inoue, Koji Kai, 1999, Proceedings Fifth International Symposium on High-Performance Computer Architecture.

High-Performance/Low-Power Cache Architectures for Merged DRAM/Logic LSIs

Koji Inoue, Tohru Ishihara, 井上 弘士, 2001 .

INVITED PAPER Special Section on Circuits and Design Techniques for Advanced Large Scale Integration Prospective Silicon Applications and Technologies in 2025

Minoru Fujishima, Koji Kai, M. Fujishima, 2011 .