M. Qazi

A statistical study of magnetic tunnel junctions for high-density spin torque transfer-MRAM (STT-MRAM)

S. Le, S. Kanakasabapathy, J. Nowak, 2008, 2008 IEEE International Electron Devices Meeting.

Breaking the simulation barrier: SRAM evaluation through norm minimization

Lara Dolecek, Anantha P. Chandrakasan, Devavrat Shah, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

40 . 4 fJ / bit / mm Low-Swing On-Chip Signaling with Self-Resetting Logic Repeaters Embedded within a Mesh NoC in 45 nm SOI CMOS

A. Chandrakasan, L. Peh, M. Qazi, 2012 .

A 4kb memory array for MRAM development

Masood Qazi, M. Qazi, 2007 .

A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems

Anantha Chandrakasan, Ajith Amerasekera, Masood Qazi, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A Low-Voltage 1 Mb FRAM in 0.13 $\mu$m CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin

Anantha Chandrakasan, Masood Qazi, Michael Clinton, 2012, IEEE Journal of Solid-State Circuits.

Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis

Lara Dolecek, Devavrat Shah, Anantha Chandrakasan, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Breaking the simulation barrier: SRAM evaluation through norm minimization

D. Shah, A. Chandrakasan, L. Dolecek, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Low-Swing Signaling on Monolithically Integrated Global Graphene Interconnects

Kyeong-Jae Lee, Jing Kong, Anantha P Chandrakasan, 2010, IEEE Transactions on Electron Devices.

Challenges and Directions for Low-Voltage SRAM

Anantha Chandrakasan, Mahmut E. Sinangil, Masood Qazi, 2011, IEEE Design & Test of Computers.