J. DeBrosse

A statistical study of magnetic tunnel junctions for high-density spin torque transfer-MRAM (STT-MRAM)

S. Le, S. Kanakasabapathy, J. Nowak, 2008, 2008 IEEE International Electron Devices Meeting.

Fault-tolerant designs for 256 Mb DRAM

John K. DeBrosse, Toshiaki Kirihata, Matthew R. Wordeman, 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

A Study of Write Margin of Spin Torque Transfer Magnetic Random Access Memory Technology

Tom Zhong, Terry Torng, Tai Min, 2010, IEEE Transactions on Magnetics.

Challenges and future directions for the scaling of dynamic random-access memory (DRAM)

Robert H. Dennard, Gary B. Bronner, John K. DeBrosse, 2002, IBM J. Res. Dev..

A 14 nm Embedded STT-MRAM CMOS Technology

T. Standaert, D. Edelstein, R. Johnson, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

A high-speed 128-kb MRAM core for future universal memory applications

H. Hoenigschmid, D. Casarotto, G. Muller, 2004, IEEE Journal of Solid-State Circuits.

Design considerations for MRAM

John K. DeBrosse, William J. Gallagher, Mark A. Wood, 2006, IBM J. Res. Dev..

Demonstration of chip level writability, endurance and data retention of an entire 8Mb STT-MRAM array

W. J. Gallagher, T. Torng, J. DeBrosse, 2013, 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

A high-speed 128 Kbit MRAM core for future universal memory applications

H. Hoenigschmid, D. Casarotto, G. Muller, 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

The evolution of IBM CMOS DRAM technology

John K. DeBrosse, Steven H. Voldman, James S. Nakos, 1995, IBM J. Res. Dev..

Floating-body concerns for SOI dynamic random access memory (DRAM)

Howard Leo Kalter, Jack A. Mandelman, Robert H. Dennard, 1996, 1996 IEEE International SOI Conference Proceedings.