T. Maffitt

A statistical study of magnetic tunnel junctions for high-density spin torque transfer-MRAM (STT-MRAM)

S. Le, S. Kanakasabapathy, J. Nowak, 2008, 2008 IEEE International Electron Devices Meeting.

A Study of Write Margin of Spin Torque Transfer Magnetic Random Access Memory Technology

Tom Zhong, Terry Torng, Tai Min, 2010, IEEE Transactions on Magnetics.

1Mb 0.41 µm2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing

Peilin Song, Takeshi Nishida, Scott Lewis, 2013, 2013 Symposium on VLSI Circuits.

A 14 nm Embedded STT-MRAM CMOS Technology

T. Standaert, D. Edelstein, R. Johnson, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

A Double-Data- Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read -Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications

Chung Lam, Scott C. Lewis, Yutaka Nakamura, 2016, 2016 IEEE 8th International Memory Workshop (IMW).

Design considerations for MRAM

John K. DeBrosse, William J. Gallagher, Mark A. Wood, 2006, IBM J. Res. Dev..

Demonstration of chip level writability, endurance and data retention of an entire 8Mb STT-MRAM array

W. J. Gallagher, T. Torng, J. DeBrosse, 2013, 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

A 256-Mcell Phase-Change Memory Chip Operating at $2{+}$ Bit/Cell

Scott C. Lewis, Christoph Hagleitner, Evangelos Eleftheriou, 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

12.4 1.4Gsearch/s 2Mb/mm2 TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%

Igor Arsovski, Robert M. Houle, Steven Burns, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).