S. Seo

发表

Effects of overlayers on electromigration reliability improvement for Cu/low K interconnects

D. Restaino, A. Simon, M. Krishnan, 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

L. H. Vanamurth, D. Yang, T. Adam, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

T. Adam, T. Standaert, M. Khare, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain

T. Adam, J. Holt, B. Haran, 2006, 2009 Symposium on VLSI Technology.

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

D. Corliss, T. Standaert, R. Wong, 2017, 2017 Symposium on VLSI Technology.

Tantalum Nitride Films Grown by Inorganic Low Temperature Thermal Chemical Vapor Deposition Diffusion Barrier Properties in Copper Metallization

G. G. Peterson, H. Frisch, A. Kaloyeros, 1999 .

Study of Electrochemical Deposition of Copper and Microstructure Evolution in Fine Lines

Timothy C. Stoner, S. Grunow, S. Seo, 1999 .

Atom motion of Cu and Co in Cu damascene lines with a CoWP cap

Robert Rosenberg, S. T. Chen, C-K. Hu, 2004 .

Control of the hydrogen content of diamond-like carbon films deposited using unbalanced magnetron sputtering

S. Seo, D. Ingram, 1996 .

CMP Challenges for Advanced Technology Nodes

R. Patlolla, J. Wynne, D. Canaperi, 2017 .

Electromigration Cu mass flow in Cu interconnections

Robert Rosenberg, Andrew H. Simon, S. T. Chen, 2006 .

Effect of substrate bias on the properties of diamondlike carbon films deposited using unbalanced magnetron sputtering

H. Richardson, S. Seo, D. Ingram, 1995 .

Resistive Memory Process Optimization for High Resistance Switching Toward Scalable Analog Compute Technology for Deep Learning

M. Rasch, W. Haensch, V. Narayanan, 2021, IEEE Electron Device Letters.

Thermal Stability of Copper Contact Metallization Using Ru-Containing Liner

C. Hu, B. Haran, D. Canaperi, 2011 .

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

B. Lherron, D. Chanemougame, P. Oldiges, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Fine structures of valence-band, x-ray-excited Auger electron, and plasmon energy loss spectra of diamondlike carbon films obtained using x-ray photoelectron spectroscopy

S. Seo, D. Ingram, 1997 .

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

P. Oldiges, C. Park, N. Loubet, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Full metal gate with borderless contact for 14 nm and beyond

B. Haran, V. Narayanan, J. Bruley, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

B. Jagannathan, N. Loubet, P. Kulkarni, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Deposition of barrier layer and CVD copper under no exposed wafer conditions: adhesion performance and process integration

A. Kaloyeros, D. Manger, S. Seo, 1997, European Workshop Materials for Advanced Metallization,.

Deep learning acceleration in 14nm CMOS compatible ReRAM array: device, material and algorithm co-optimization

M. Rasch, V. Narayanan, R. Johnson, 2022, 2022 International Electron Devices Meeting (IEDM).