Kai-Shin Li

发表

Utilizing Sub-5 nm sidewall electrode technology for atomic-scale resistive memory fabrication

Y. J. Chen, C. C. Chen, C. H. Lin, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Nonvolatile molecular memory with the multilevel states based on MoS2 nanochannel field effect transistor through tuning gate voltage to control molecular configurations

T. Hou, C. Su, Kai-Shin Li, 2020, Nanotechnology.

Suppression of short channel effects in FinFETs using crystalline ZrO2 high-K/Al2O3 buffer layer gate stack for low power device applications

Min-Cheng Chen, Kai-Shin Li, Miin-Jang Chen, 2018 .

Polarity-controllable MoS2 transistor for adjustable complementary logic inverter applications

Y. Su, Kai-Shin Li, Yann-Wen Lan, 2020 .

Twisted Light-Induced Photocurrent in a Silicon Nanowire Field-Effect Transistor.

Tilo H. Yang, Kai-Shin Li, Yann-Wen Lan, 2022, ACS nano.

Analytical Modeling of Read-Induced SET-State Conductance Change in a Hafnium-Oxide Resistive Switching Device

Tahui Wang, Kai-Shin Li, Chao-Cheng Lin, 2020, IEEE Transactions on Electron Devices.

Monolithic 3D SRAM-CIM Macro Fabricated with BEOL Gate-All-Around MOSFETs

Kun-Ming Chen, G. Huang, C. Hu, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Sub-60mV-swing negative-capacitance FinFET without hysteresis

Chenming Hu, Sayeef Salahuddin, Kai-Shin Li, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Four-layer 3D vertical RRAM integrated with FinFET as a versatile computing unit for brain-inspired cognitive information processing

S. Burc Eryilmaz, Min-Cheng Chen, Jia-Min Shieh, 2016, 2016 IEEE Symposium on VLSI Technology.

Optimizing the Ferroelectric Properties of Hf1–xZrxO2 Films via Crystal Orientation

Kai-Shin Li, Jhih-Min Lin, Y. Tseng, 2023, ACS Applied Electronic Materials.

Monolithic 3D integration of back-end compatible 2D material FET on Si FinFET

C. Su, Kai-Shin Li, Lain‐Jong Li, 2023, npj 2D Materials and Applications.

Scalable fabrication of a complementary logic inverter based on MoS2 fin-shaped field effect transistors

Ming-Yang Li, Lain-Jong Li, Kai-Shin Li, 2019, Nanoscale Horizons.

Effective N-methyl-2-pyrrolidone wet cleaning for fabricating high-performance monolayer MoS2 transistors

T. Hou, C. Su, Kai-Shin Li, 2018, Nano Reseach.

High-Frequency Graphene Base Hot-Electron Transistor.

C. Kuan, Kai-Shin Li, Hung‐Yu Lin, 2021, ACS Nano.

Ferroelectric HfZrOx FETs on SOI Substrate With Reverse-DIBL (Drain-Induced Barrier Lowering) and NDR (Negative Differential Resistance)

C.-Y. Liao, S. Gu, G.-Y. Siang, 2018, IEEE Journal of the Electron Devices Society.

Improved Electrical Characteristics of Bulk FinFETs With SiGe Super-Lattice-Like Buried Channel

G. Luo, Kai-Shin Li, K. Chang-Liao, 2019, IEEE Electron Device Letters.

Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiO $_{{x}}$ /Si Substrates Using Area-Selective CVD Technology

Kai-Shin Li, T. Lai, J. Shieh, 2019, IEEE Transactions on Electron Devices.

Damage-Free ALD Blocking Oxide Layer on Functionalized Graphene Nanosheets as Nonvolatile Memories

W. Yeh, Kai-Shin Li, Han-Hsiang Tai, 2019, IEEE Transactions on Electron Devices.

First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrate

Kai-Shin Li, T. Lai, J. Shieh, 2019, 2019 Symposium on VLSI Technology.

Spontaneously induced magnetic anisotropy in an ultrathin Co/MoS2 heterojunction.

Kai-Shin Li, C. Tusche, I. Cojocariu, 2020, Nanoscale horizons.

A numerical study of Si-TMD contact with n/p type operation and interface barrier reduction for sub-5 nm monolayer MoS2 FET

C. Hu, W. Yeh, Tahui Wang, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

First Demonstration of Interface-Enhanced SAF Enabling 400°C-Robust 42 nm p-SOT-MTJ Cells with STT-Assisted Field-Free Switching and Composite Channels

C. Liu, Cho-Lun Hsu, D. Tang, 2021, 2021 Symposium on VLSI Technology.

Demonstration of High Endurance and Retention Spin-Transfer-Torque-Assisted Field-Free Perpendicular Spin-Orbit Torque Cells by an Etch-Stop-on-MgO Process

D. Tang, Kai-Shin Li, J. Shieh, 2022, IEEE Electron Device Letters.

Thermally Robust Perpendicular SOT-MTJ Memory Cells With STT-Assisted Field-Free Switching

J. Sun, D. Tang, Kai-Shin Li, 2021, IEEE Transactions on Electron Devices.

MoS2 U-shape MOSFET with 10 nm channel length and poly-Si source/drain serving as seed for full wafer CVD MoS2 availability

Jia-Min Shieh, Yu-Lun Chueh, Chenming Hu, 2016, 2016 IEEE Symposium on VLSI Technology.

A Dual-Split-Controlled 4P2N 6T SRAM in Monolithic 3D-ICs With Enhanced Read Speed and Cell Stability for IoT Applications

Meng-Fan Chang, Guo-Wei Huang, Hiroyuki Yamauchi, 2018, IEEE Electron Device Letters.

Negative-Capacitance FinFET Inverter, Ring Oscillator, SRAM Cell, and Ft

Jia-Min Shieh, Chenming Hu, Wen-Cheng Chiu, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Ultra-Low Power 3D NC-FinFET-based Monolithic 3D+ -IC with Computing-in-Memory for Intelligent IoT Devices

Guo-Wei Huang, Jia-Min Shieh, Chih-Chao Yang, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

TMD FinFET with 4 nm thin body and back gate control for future low power technology

Yao-Jen Lee, C. Hu, W. Yeh, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Low-cost and TSV-free monolithic 3D-IC with heterogeneous integration of logic, memory and sensor analogy circuitry for Internet of Things

Meng-Fan Chang, Guo-Wei Huang, Ting-Jen Hsueh, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

First Demonstration of Ultrafast Laser Annealed Monolithic 3D Gate-All-Around CMOS Logic and FeFET Memory with Near-Memory-Computing Macro

Kun-Ming Chen, G. Huang, C. Hu, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Read circuits for resistive memory (ReRAM) and memristor-based nonvolatile Logics

Meng-Fan Chang, Jia-Min Shieh, Albert Lee, 2015, The 20th Asia and South Pacific Design Automation Conference.