T. Lai

发表

Utilizing Sub-5 nm sidewall electrode technology for atomic-scale resistive memory fabrication

Y. J. Chen, C. C. Chen, C. H. Lin, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Non-Faradaic electrical impedimetric investigation of the interfacial effects of neuronal cell growth and differentiation on silicon nanowire transistors.

T. Lai, Shu-Ping Lin, L. U. Vinzons, 2015, ACS applied materials & interfaces.

Field emission properties of gold nanoparticle-decorated ZnO nanopillars.

T. Lai, J. Juang, Yuan-Ming Chang, 2012, ACS applied materials & interfaces.

Effect of Compressive Stress on Evolution and Healing Kinetics of Artificial Voids in Highly (111)-Oriented Cu-Cu Wafer Bonding at 300 °C

T. Lai, Y. S. Wu, Y. H. Wang, 2021 .

Bonding Mechanisms of Roughened Nanotwinned-Cu Surface at Temperature as Low as 120 °C

T. Lai, Y. S. Wu, Y. H. Wang, 2020, ECS Journal of Solid State Science and Technology.

Broadband Omnidirectional Light Trapping in Gold-Decorated ZnO Nanopillar Arrays.

T. Lai, J. Juang, Yen‐Fu Lin, 2017, ACS applied materials & interfaces.

Investigation into the Effect of Varied Functional Biointerfaces on Silicon Nanowire MOSFETs

Shu-Ping Lin, Mao-Chen Liu, Tung-Yen Lai, 2012, Sensors.

Moisture sensitive field effect transistors using SiO 2 /Si 3 N 4 /Al 2 O 3 gate structure

T. Lai, K. Hara, S. Chakraborty, 1999 .

The effect of varied functional biointerfaces on the sensitivity of silicon nanowire MOSFET

Mao-Chen Liu, T. Lai, Shu-Ping Lin, 2012, 2012 IEEE-EMBS Conference on Biomedical Engineering and Sciences.

Impedimetric investigation of dual electrical properties of reduced graphene-oxide-based biosensors in the detection of dopamine

Shu-Ping Lin, Tung-Yen Lai, Jhong-Yi Ciou, 2017, 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiO $_{{x}}$ /Si Substrates Using Area-Selective CVD Technology

Kai-Shin Li, T. Lai, J. Shieh, 2019, IEEE Transactions on Electron Devices.

First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrate

Kai-Shin Li, T. Lai, J. Shieh, 2019, 2019 Symposium on VLSI Technology.

A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin

Chenming Hu, ChiaHua Ho, Yi-Ping Hsieh, 2013, 2013 Symposium on VLSI Technology.

Broadband Omnidirectional Light Trapping in Gold-Decorated ZnO Nanopillar Arrays.

T. Lai, J. Juang, Yen‐Fu Lin, 2017, ACS applied materials & interfaces.

Interpretation of biosensing technology in cell-coupled silicon nanowire transistors via impedance spectra

T. Lai, Shu-Ping Lin, L. U. Vinzons, 2022, Materials Letters.