A. Pouydebasque

发表

Advances in 3D CMOS sequential integration

A. Toffoli, O. Cueto, O. Faynot, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Localized ultra-thin GeOI: An innovative approach to germanium channel MOSFETs on bulk Si substrates

G. Ghibaudo, T. Skotnicki, S. Monfray, 2008, 2008 IEEE International Electron Devices Meeting.

Unexpected mobility degradation for very short devices : A new challenge for CMOS scaling

G. Ghibaudo, T. Skotnicki, R. Gwoziecki, 2006, 2006 International Electron Devices Meeting.

3D CMOS integration: Introduction of dynamic coupling and application to compact and robust 4T SRAM

S. Deleonibus, P. Batude, M. Vinet, 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

Enabling 3D Monolithic Integration

H. Grampeix, S. Deleonibus, P. Batude, 2008 .

3D monolithic integration: Technological challenges and electrical results

H. Grampeix, O. Faynot, S. Deleonibus, 2011 .

High Threshold Voltage Matching Performance on Gate-All-Around MOSFET

G. Ghibaudo, T. Skotnicki, A. Cathignol, 2007, 2006 European Solid-State Device Research Conference.

Impact of scaling on electrostatics of Germanium-channel MOSFET — analytical study

G. Ghibaudo, T. Skotnicki, S. Monfray, 2008, 2008 IEEE Silicon Nanoelectronics Workshop.

GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current

O. Faynot, M. Vinet, C. Tabone, 2010, IEEE Electron Device Letters.

New materials and device architectures for the end-of-roadmap CMOS nodes

Stephane Monfray, Claire Fenouillet-Beranger, Frederic Boeuf, 2005 .

Fabrication and characterization of a new varifocal liquid lens with embedded PZT actuators for high optical performances

S. Fanget, A. Pouydebasque, M. Allain, 2015, 2015 28th IEEE International Conference on Micro Electro Mechanical Systems (MEMS).

Germanium on insulator and new 3D architectures opportunities for integration

J. Hartmann, P. Batude, M. Vinet, 2010 .

Using MASTAR as a Pre-SPICE Model Generator for Early Technology Assessment and Circuit Simulation

T. Skotnicki, E. Josse, F. Boeuf, 2006 .

20nm gate length trigate pFETs on strained SGOI for high performance CMOS

X. Garros, O. Faynot, P. Batude, 2010, 2010 Symposium on VLSI Technology.

Ion-Ioff performance analysis of FDSOI MOSFETs with low processing temperature

M. Mouis, P. Batude, B. Previtali, 2010 .

Experimental Evidence of Sidewall Enhanced Transport Properties of Mesa-Isolated (001) Germanium-On-Insulator pMOSFETs

H. Grampeix, J. Hartmann, F. Allain, 2009, IEEE Transactions on Electron Devices.

Semi-classical orbits in a caterpillar like Sinaı̈ billiard

A. Pouydebasque, D. Maude, Z. Kvon, 2000 .

Si/SiGe Epitaxy: a Ubiquitous Process for Advanced Electronics

P. Chevalier, T. Skotnicki, S. Monfray, 2007, 2007 IEEE International Electron Devices Meeting.

Gate-All-Around technology: taking advantage of ballistic transport ?

G. Ghibaudo, T. Skotnicki, S. Monfray, 2009, ESSDERC 2009.

Experimental Quantification of the Residual Stress of Thin Membrane Materials in MEMS Devices Using Point Deflection

S. Moreau, S. Fanget, A. Pouydebasque, 2014 .

Varifocal liquid lenses with integrated actuator, high focusing power and low operating voltage fabricated on 200 mm wafers

N. Sillon, A. Pouydebasque, C. Kopp, 2011 .

Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia

T. Skotnicki, S. Monfray, F. Arnaud, 2008, IEEE Transactions on Electron Devices.

High-Performance High-$K$/Metal Planar Self-Aligned Gate-All-Around CMOS Devices

T. Skotnicki, F. Leverd, D. Dutartre, 2008, IEEE Transactions on Nanotechnology.

Optimized nickel silicide process formation for high performance sub-65nm CMOS nodes

F. Wacquant, A. Pouydebasque, V. Carron, 2004 .

Advances, challenges and opportunities in 3D CMOS sequential integration

J. Mazurier, O. Faynot, P. Batude, 2011, 2011 International Electron Devices Meeting.

Thermomagnetic effect in a two-dimensional electron system with an asymmetric quantizing potential

A. Pouydebasque, D. Maude, J. Portal, 2000 .

High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate

X. Garros, G. Reimbold, Emmanuel Augendre, 2009 .

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

G. Le Carval, M. Vinet, S. Deleonibus, 2008 .

Sub-100nm high-K metal gate GeOI pMOSFETs performance: Impact of the Ge channel orientation and of the source injection velocity

M. Vinet, J.-M. Hartmann, E. Augendre, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

The Ge condensation technique: A solution for planar SOI/GeOI co-integration for advanced CMOS technologies?

Yves Morand, Yves Campidelli, Sorin Cristoloveanu, 2008 .

A new experimental methodology using point deflection to quantify residual stress of thin polymer membrane materials in MEMS devices

Stéphane Moreau, Stephane Fanget, Christophe Poulain, 2013, The 8th Annual IEEE International Conference on Nano/Micro Engineered and Molecular Systems.

Enabling technologies for advanced wafer level camera integration

S. Moreau, N. Sillon, G. Simon, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Thin varifocal liquid lenses actuated below 10V for mobile phone cameras

Christophe Kopp, Sofiane Soulimane, Sébastien Bolis, 2012, Photonics West - Micro and Nano Fabricated Electromechanical and Optical Components.

Ultra low cost wafer level via filling and interconnection using conductive polymer

R. Anciant, N. Sillon, A. Pouydebasque, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

Process optimization and performance analysis of an electrostatically actuated varifocal liquid lens

C. Kopp, A. Pouydebasque, N. Sillon, 2011, 2011 16th International Solid-State Sensors, Actuators and Microsystems Conference.

GeOI and SOI 3D monolithic cell integrations for high density applications

X. Garros, O. Rozeau, O. Faynot, 2006, 2009 Symposium on VLSI Technology.