V. Viñals

发表

The reuse cache: Downsizing the shared last-level cache

Víctor Viñals, José María Llabería, Jorge Albericio, 2013, 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

RR-09-01 ( 27 / 03 / 2009 ) Improving the use of instruction cache-locking methods in multitasking real-time systems

V. Viñals, J. L. Villarroel, J. Segarra, 2009 .

A Two-Level STB in a Multibanked L 1 Cache Framework

P. Ibáñez, V. Viñals, J. Llabería, 2022 .

Limits on Early Release of Physical Registers

M. Valero, V. Viñals, Jesús Alastruey, 2022 .

Architecture and Code Optimization

Francisco J. Cazorla, Yunheung Paek, Mateo Valero, 2011 .

Berti: an Accurate Local-Delta Data Prefetcher

Alberto Ros, P. Ibáñez, V. Viñals, 2022, 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO).

peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter

Rubén Gran Tejero, A. Valero, V. Viñals, 2022, 2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS).

Hardware schemes for early register release

Mateo Valero, Víctor Viñals, Teresa Monreal Arnal, 2002, Proceedings International Conference on Parallel Processing.

Energy-efficient Management of Reconfigurable Computers

Carl J. Mauer, Philip M. Wells, Milo M. K. Martin, 2016 .

Late allocation and early release of physical registers

Mateo Valero, José González, Víctor Viñals, 2004, IEEE Transactions on Computers.

Tradeoffs in buffering memory state for thread-level speculation in multiprocessors

Josep Torrellas, Lawrence Rauchwerger, Milos Prvulovic, 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

Store buffer design in first-level multibanked data caches

Víctor Viñals, José María Llabería, Pablo Ibáñez, 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

Exposing Abstraction-Level Interactions with a Parallel Ray Tracer

Ana Cristina Murillo, Víctor Viñals, Joaquín Ezpeleta, 2019, WCAE@ISCA.

Characterization and improvement of load/store cache-based prefetching

Víctor Viñals, María Jesús Garzarán, Pablo Ibáñez, 1998, ICS '98.

Capturing the sensitivity of optical network quality metrics to its network interface parameters

Davide Bertozzi, Marta Ortín-Obón, Luca Ramini, 2014, Concurr. Comput. Pract. Exp..

A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip

Davide Bertozzi, Marta Ortín-Obón, Luca Ramini, 2014, GLSVLSI '14.

LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors

Giorgos Dimitrakopoulos, Víctor Viñals, Teresa Monreal Arnal, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Software Demand, Hardware Supply

Víctor Viñals, Jesús Alastruey-Benedé, Pablo Ibáñez, 2006, IEEE Micro.

ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache

Víctor Viñals, José María Llabería, Jorge Albericio, 2012, TACO.

Execution Path Pruning for WCET Analysis

Víctor Viñals, Juan Segarra, Jose Luis Villarroel, 2006 .

Light NUCA: a proposal for bridging the inter-cache latency gap

Víctor Viñals, Ramón Beivide, Teresa Monreal Arnal, 2009, DATE '09.

Effcient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers

P. Ibáñez, V. Viñals, J. Llabería, 2012, Journal of Computer Science and Technology.

Characterization of Apache web server with Specweb2005

Víctor Viñals, Per Stenström, Ana Bosque, 2007, MEDEA '07.

A proposal to introduce power and energy notions in computer architecture laboratories

Víctor Viñals, Darío Suárez Gracia, Alicia Asín Pérez, 2007, WCAE '07.

Filtering Directory Lookups in CMPs with Write-Through Caches

Víctor Viñals, José María Llabería, Pablo Ibáñez, 2011, Euro-Par.

Near-optimal replacement policies for shared caches in multicore processors

Víctor Viñals, José María Llabería, Teresa Monreal Arnal, 2021, The Journal of Supercomputing.